TCAD Performance Analysis of a Symmetrical Double Gate Non-Aligned Junction FET Device with High and Low Dielectric Gate Oxide in Sub-100 nm Regime

ABSTRACT This paper presents 2D-Sentaurus TCAD tool results of a Non-aligned Double Gate Junction N-Channel Field Effect Transistor (NADGNFET) device; the response analysis of device to gate oxide dielectric materials, i.e. silicon dioxide (SiO2) and hafnium dioxide (HfO2), is also presented. The NADGNFET in 90 nm device length is the proposal of this work to improve the second-order effects as well transistor non-linear performance at radio frequency (RF). A non-aligned device in this work consists of two gates extending to the source and drain region with 44.44% channel overlap in total device length. As compared to a full overlap device, the present device has shown better results in Analog Figure of Merit (FOM) and RF parameters like: ION current, ION/IOFF ratio, DIBL (Drain Induced Barrier lowering), SS (Subthreshold Swing), Intrinsic gain (AVO), Transconductance Generation Factor (TGF), Transconductance Frequency Product (TFP), Cut-off frequency (fT), Intercepted Input Power-3 (IIP3) and Intermodulation Distortion power-3 (IMD3). The use of dielectric material with high dielectric constant (HfO2, k = 24) in gate oxide reduces DIBL by 50%, increases the ION/IOFF ratio by 59.1%, increases the Intrinsic gain by 50% compared to low-k dielectric constant (SiO2, k = 3.9). However, results also shows that high-frequency parameters’ results were better with low-k dielectric constant. This gives a trade-off in device application.