Alok Mishra, Urvashi Chopra, Vaithiyanathan D., B. Kaur
{"title":"一种低功耗高速单相时钟电平恢复16T主从触发器","authors":"Alok Mishra, Urvashi Chopra, Vaithiyanathan D., B. Kaur","doi":"10.1108/cw-08-2020-0196","DOIUrl":null,"url":null,"abstract":"\nPurpose\nA low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital circuit. The sequential circuits consist of a basic data storing element, a latch is used to store single bit data. The flip-flop takes a sufficient portion of the total chip area and overall power consumption as well. This study aims to the low power energy-efficient applications like laptops, mobile phones and palmtops.\n\n\nDesign/methodology/approach\nThis paper proposes a new type of flip-flop that consists of the only 16 transistors with a single-phase clock. The flip-flop has two blocks, master and slave latch. In this design, the authors have focused on only master latch, which includes a level restoring circuit. It is used to help the master latch in data retention process. The latch circuit has two inverters in back-to-back arrangement. The proposed flip-flop is implemented on 65 nm complementary metal oxide semiconductor technology using Cadence Virtuoso environment and compared with other reported flip-flops.\n\n\nFindings\nThe proposed flip-flop architecture outperformed the peak percentage, i.e. 79.25% as compared to transmission gate flip-flop and a minimum of 20.02% compared to 18 T true single phase clocking (TSPC) improvement in terms of power. It also improved C to Q delay and power delay product. In addition, by reducing the number of transistors the total area of the proposed flip-flop is reduced by a minimum of 13.76% with respect to 18TSPC and existing flip-flop. For reliability checking the Monte Carlo simulation is performed for thousand samples and it is compared with the recently reported 18TSPC flip-flop.\n\n\nOriginality/value\nThis work is tested by using a test circuit with a load capacitor of 0.2 fF. The proposed work uses a new topology to work as master-slave. Power consumption of this technique is very less and it is best suitable for low power applications. This circuit is working properly up to 2 GHz frequency.\n","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.8000,"publicationDate":"2022-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A low power high speed single phase clock level restoring 16T master-slave flip-flop\",\"authors\":\"Alok Mishra, Urvashi Chopra, Vaithiyanathan D., B. Kaur\",\"doi\":\"10.1108/cw-08-2020-0196\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"\\nPurpose\\nA low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital circuit. The sequential circuits consist of a basic data storing element, a latch is used to store single bit data. The flip-flop takes a sufficient portion of the total chip area and overall power consumption as well. This study aims to the low power energy-efficient applications like laptops, mobile phones and palmtops.\\n\\n\\nDesign/methodology/approach\\nThis paper proposes a new type of flip-flop that consists of the only 16 transistors with a single-phase clock. The flip-flop has two blocks, master and slave latch. In this design, the authors have focused on only master latch, which includes a level restoring circuit. It is used to help the master latch in data retention process. The latch circuit has two inverters in back-to-back arrangement. The proposed flip-flop is implemented on 65 nm complementary metal oxide semiconductor technology using Cadence Virtuoso environment and compared with other reported flip-flops.\\n\\n\\nFindings\\nThe proposed flip-flop architecture outperformed the peak percentage, i.e. 79.25% as compared to transmission gate flip-flop and a minimum of 20.02% compared to 18 T true single phase clocking (TSPC) improvement in terms of power. It also improved C to Q delay and power delay product. In addition, by reducing the number of transistors the total area of the proposed flip-flop is reduced by a minimum of 13.76% with respect to 18TSPC and existing flip-flop. For reliability checking the Monte Carlo simulation is performed for thousand samples and it is compared with the recently reported 18TSPC flip-flop.\\n\\n\\nOriginality/value\\nThis work is tested by using a test circuit with a load capacitor of 0.2 fF. The proposed work uses a new topology to work as master-slave. Power consumption of this technique is very less and it is best suitable for low power applications. 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A low power high speed single phase clock level restoring 16T master-slave flip-flop
Purpose
A low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital circuit. The sequential circuits consist of a basic data storing element, a latch is used to store single bit data. The flip-flop takes a sufficient portion of the total chip area and overall power consumption as well. This study aims to the low power energy-efficient applications like laptops, mobile phones and palmtops.
Design/methodology/approach
This paper proposes a new type of flip-flop that consists of the only 16 transistors with a single-phase clock. The flip-flop has two blocks, master and slave latch. In this design, the authors have focused on only master latch, which includes a level restoring circuit. It is used to help the master latch in data retention process. The latch circuit has two inverters in back-to-back arrangement. The proposed flip-flop is implemented on 65 nm complementary metal oxide semiconductor technology using Cadence Virtuoso environment and compared with other reported flip-flops.
Findings
The proposed flip-flop architecture outperformed the peak percentage, i.e. 79.25% as compared to transmission gate flip-flop and a minimum of 20.02% compared to 18 T true single phase clocking (TSPC) improvement in terms of power. It also improved C to Q delay and power delay product. In addition, by reducing the number of transistors the total area of the proposed flip-flop is reduced by a minimum of 13.76% with respect to 18TSPC and existing flip-flop. For reliability checking the Monte Carlo simulation is performed for thousand samples and it is compared with the recently reported 18TSPC flip-flop.
Originality/value
This work is tested by using a test circuit with a load capacitor of 0.2 fF. The proposed work uses a new topology to work as master-slave. Power consumption of this technique is very less and it is best suitable for low power applications. This circuit is working properly up to 2 GHz frequency.
期刊介绍:
Circuit World is a platform for state of the art, technical papers and editorials in the areas of electronics circuit, component, assembly, and product design, manufacture, test, and use, including quality, reliability and safety. The journal comprises the multidisciplinary study of the various theories, methodologies, technologies, processes and applications relating to todays and future electronics. Circuit World provides a comprehensive and authoritative information source for research, application and current awareness purposes.
Circuit World covers a broad range of topics, including:
• Circuit theory, design methodology, analysis and simulation
• Digital, analog, microwave and optoelectronic integrated circuits
• Semiconductors, passives, connectors and sensors
• Electronic packaging of components, assemblies and products
• PCB design technologies and processes (controlled impedance, high-speed PCBs, laminates and lamination, laser processes and drilling, moulded interconnect devices, multilayer boards, optical PCBs, single- and double-sided boards, soldering and solderable finishes)
• Design for X (including manufacturability, quality, reliability, maintainability, sustainment, safety, reuse, disposal)
• Internet of Things (IoT).