Reduced ordered binary decision diagram-based combinational circuit synthesis for optimising area, power and temperature

In this paper, an attempt is made to reduce the rise in circuit temperature by optimising power-density during logic synthesis level. Reduced ordered binary decision diagram (ROBDD) being canonical in nature makes a suitable choice of logic realisation in this work. ROBDD is used here not only to reduce area (node) but also the possibility of reducing power and temperature (power-density) is explored. In this work, a genetic algorithm based approach is presented to determine a suitable variable ordering during the formation of the ROBDD for its thermal-aware realisation considering other parameters like area and power without performance degradation. The proposed approach shows more than 33% savings in area and power, and 5.61% savings in power-density with respect to initial ROBDD representation of LGSynth93 benchmark circuits. Actual on-chip area, power dissipation and the absolute value of temperature are calculated using CADENCE and HotSpot tool to validate the power-density based results.