Systematic design strategy for DPL-based ternary logic circuit

This work proposes novel strategy to design 2-input ternary (base-3) logic circuits using double pass-transistor logic (DPL). The concept has been explored with respect to 2-input TXOR gate. The circuit diagram of proposed DPL-based TXOR, TAND and TOR logic gate is presented. The proposed T-Cells are designed and optimised using BSIM3 device model with 1.8 V supply rail and at 25°C temperature on TSMC 0.18 µm CMOS technology. The transient response from T-Spice simulatio is validated and the speed-power performance is recorded. Next, the 2:9 ternary decoder based on proposed idea has been explained. The decoder circuit is also designed with 1.8 V supply rail at 25°C temperature on TSMC 0.18 µm CMOS technology. The trit value '0', '1' and '2' are represented with 0 V, 0.9 V and 1.8 V respectively. As per simulation result the proposed 2:9 ternary decoder dissipates 383.57 µW average power and takes 64.87 ps to generate final output.