Electro-thermal assessment of heterojunction tunnel-FET for low-power digital circuits

To overcome the fundamental limitations of conventional MOSFETs, tunnel field effect transistors (TFETs) with strained-SiGe channel (via heterogeneous integration) may be used and is demonstrated using TCAD simulations. We mainly focus on the design and implementation of silicon-germanium (SiGe)-based tunnel field effect transistor, aiming to reduce the device operation voltage down to below 0.5 V. Physics-based electro-thermal simulations are performed for evaluating the self-heating (temperature rise) in the devices. We present the results of the electro-thermal analysis supported by effective 2D and 3D device simulations. Performance improvement in drain current as high as 200% has been achieved.