{"title":"支持SOC设计、验证和重用的前端自动化工具。","authors":"Xiao-lang Yan, Long-li Yu, Jie-bing Wang","doi":"10.1631/jzus.2004.1102","DOIUrl":null,"url":null,"abstract":"<p><p>This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog code by more than a factor of 5, increase the efficiency of the front-end design, reduce the bug rate significantly. This tool can be used to enhance the reusability of an intellectual property model, and facilitate porting design for different platforms.</p>","PeriodicalId":85042,"journal":{"name":"Journal of Zhejiang University. Science","volume":"5 9","pages":"1102-5"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1631/jzus.2004.1102","citationCount":"1","resultStr":"{\"title\":\"A front-end automation tool supporting design, verification and reuse of SOC.\",\"authors\":\"Xiao-lang Yan, Long-li Yu, Jie-bing Wang\",\"doi\":\"10.1631/jzus.2004.1102\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<p><p>This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog code by more than a factor of 5, increase the efficiency of the front-end design, reduce the bug rate significantly. This tool can be used to enhance the reusability of an intellectual property model, and facilitate porting design for different platforms.</p>\",\"PeriodicalId\":85042,\"journal\":{\"name\":\"Journal of Zhejiang University. Science\",\"volume\":\"5 9\",\"pages\":\"1102-5\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://sci-hub-pdf.com/10.1631/jzus.2004.1102\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Journal of Zhejiang University. Science\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1631/jzus.2004.1102\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Zhejiang University. Science","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1631/jzus.2004.1102","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A front-end automation tool supporting design, verification and reuse of SOC.
This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog code by more than a factor of 5, increase the efficiency of the front-end design, reduce the bug rate significantly. This tool can be used to enhance the reusability of an intellectual property model, and facilitate porting design for different platforms.
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