Enhanced YOLO with FPGA hardware acceleration for aluminum sheet defect detection

The leap forward in transitioning to intelligent manufacturing—particularly in the area of metal surface defect detection—has been dramatically reinforced by advances in informatization. Convolutional Neural Networks (CNNs), rooted in deep learning, have demonstrated considerable promise in image recognition tasks. However, challenges concerning resource allocation and high power consumption persist, posing notable bottlenecks for practical deployment. To address these concerns, this paper proposes an accelerator for the You-Only-Look-Once (YOLO) v4-Tiny algorithm and its implementation on a System-on-Chip (SoC) architecture. First, the k-means++ clustering algorithm is employed to reposition anchor boxes, and a hardware-friendly activation function is integrated into the model. Moreover, the Field Programmable Gate Array (FPGA) accelerates the network through computational efficiency improvements and lightweight design optimizations. To further enhance performance, the paper employs layer fusion, network parameters quantization to reduce computational complexity and resource consumption. Additionally, for memory efficiency, ping-pong buffering is proposed, significantly improving data interaction. Furthermore, throughput and area optimization are achieved using High-Level Synthesis (HLS) instructions. Ultimately, this design incorporates multi-port I/O and loop tiling strategy to further improve data processing efficiency. The tailored optimization showcases promising outcomes, maintaining a mean average precision (mAP) of 97.76 %, accompanied by a low power consumption of 2.77 W and a runtime of 0.279 s. It achieves an optimal balance of evaluation metrics, prioritizing competitive detection accuracy and low power consumption over maximal performance across all indicators. This approach fulfills industrial requirements for aluminum sheet flaw identification, demonstrating significant theoretical and practical contributions.