Optimizing the number of floorplanning layers for stacked integrated circuits based on spiking variational graph auto-encoders

As the complexity of chip design continues to increase, the stacking of multiple device layers in a three-dimensional (3D) architecture has emerged as a promising approach to improve performance, power efficiency and area (PPA). The optimization of macro-module arrangement and inter-tier connections in 3D stacked chip layout is significantly influenced by the selection of the number of layers, which affects both the feasibility of the layout optimization and the final performance of the chips. In this paper, we creatively propose the Spiking Variational Graph Auto-Encoders (S-VGAE), which aim to be applied in several varieties of stacked clustering to partition the data set comprising 22 integrated circuits. By converting graph topology into spatiotemporal pulse patterns, the Spiking Graph Convolution fundamentally enhances the representational capacity of subsequent Graph Auto-Encoders. In the layout stage for all dies, we propose the Memristive-Inspired Bottom-up Left Justified Learning (MBLJL) Strategy to determine the better performance of bi-level or tri-level stacked floorplanning layout.