Design of data access and schedule optimization for VTA compiled instruction streams

In recent years, the development and rapid implementation of convolutional neural network models have become a key research area in the field of deep learning, and model deployment schemes based on deep learning compilers have been widely studied. Acceleration of the process of convolution operations and improvement of model inference performance is one of the important research areas in the field of deep learning compilers. In this paper, based on the open source deep learning compilation framework TVM and the architecture of the deep learning accelerator VTA, we propose a minimum data access design based on the input prioritized schedule and the on-chip weight-memory reuse scheme, which provides an optimization scheme with generality for inference acceleration of convolutional neural networks. By applying the optimized schedule scheme proposed, we can avoid redundant data accesses for convolutional computation with proper shape. Comparison experiments show that the model inference time of YOLOv3 is reduced by about 10$\%$ with limited hardware resources.