Designing a QEMU plugin to profile multicore long vector RISC-V architectures: RAVE

Simulators are crucial during the development of a chip, like the RISC-V accelerator designed in the European Processor Initiative project. In this paper, we showcase the limitations of the current emulation solutions in the project and propose using QEMU with RAVE, a plugin we implement and describe in this document. This methodology can rapidly emulate and analyze applications running on the v1.0 and v0.7.1 RISC-V V-extension. Our plugin reports the vector and scalar instructions alongside useful information such as the vector-length being used, the single-element-width, and the register usage, among other vectorization metrics. We provide an API used from the emulated Application to control the RAVE plugin and the capability to generate vectorization traces that can be analyzed using Paraver. Additionally, we demonstrate the efficiency of our solution against other emulators such as Whipser, ETISS, Spike, or FPGA simulation. Finally, we describe the challenges and solutions for synchronizing and emulating multi-threaded and multi-process binaries, and evaluate the performance of RAVE running on multiple processors.