{"title":"基于载波的简化SVDPWM方法降低共模电压矢量冗余以改善四电平NPC逆变器输出电流纹波","authors":"Le Nam Pham;Quoc Dung Phan;Nho-van Nguyen","doi":"10.1109/ACCESS.2025.3589572","DOIUrl":null,"url":null,"abstract":"In this article, new fast and Three-level reduced common-mode voltage (RCMV) space vector Discontinuous pulse width modulation (SVDPWM) strategies are proposed to achieve high performance in four-level neutral point clamped (4L-NPC) inverters. Redundant reduced common-mode voltage (RCMV) vectors in the space vector diagram (SVD) of the Four-level inverter are utilized to design three discontinuous pulse width modulation (DPWM) control strategies with Three-level CMV (3L-CMV) characteristic, SVDPWM0, SVDPWM1 and HSVDPWM. The last and best one is deduced based on harmonic flux and harmonic distortion factor (HDF) analysis, to improve the output current ripple. For analysis and easy implementation, the SVPWM of the four-level inverter will be solved in the two-level SVD. A simple carrier-based PWM implementation of the RCMV SVDPWM methods will be developed to reduce the computational burden. The proposed 3L-CMV methods significantly reduce harmonic distortion compared to both Two-level CMV (2L-CMV) and Four-level CMV (4L-CMV) SVPWM methods. They exhibit a reduction in peak-to-peak CMV from approximately 40% to 60% and a lower CMV magnitude in the sampling frequency component compared to the 4L-CMV methods. As a result, the proposed system exhibits a considerable reduction in RMS leakage current. Additionally, they can achieve a reduction in switching loss up to 40% in specific conditions, offering improved efficiency compared to continuous PWM schemes.","PeriodicalId":13079,"journal":{"name":"IEEE Access","volume":"13 ","pages":"124962-124978"},"PeriodicalIF":3.4000,"publicationDate":"2025-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11082150","citationCount":"0","resultStr":"{\"title\":\"Simplified Carrier-Based SVDPWM Methods Using Reduced Common Mode Voltage Vector Redundancy for Improving Output Current Ripple in Four-Level NPC Inverter\",\"authors\":\"Le Nam Pham;Quoc Dung Phan;Nho-van Nguyen\",\"doi\":\"10.1109/ACCESS.2025.3589572\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this article, new fast and Three-level reduced common-mode voltage (RCMV) space vector Discontinuous pulse width modulation (SVDPWM) strategies are proposed to achieve high performance in four-level neutral point clamped (4L-NPC) inverters. Redundant reduced common-mode voltage (RCMV) vectors in the space vector diagram (SVD) of the Four-level inverter are utilized to design three discontinuous pulse width modulation (DPWM) control strategies with Three-level CMV (3L-CMV) characteristic, SVDPWM0, SVDPWM1 and HSVDPWM. The last and best one is deduced based on harmonic flux and harmonic distortion factor (HDF) analysis, to improve the output current ripple. For analysis and easy implementation, the SVPWM of the four-level inverter will be solved in the two-level SVD. A simple carrier-based PWM implementation of the RCMV SVDPWM methods will be developed to reduce the computational burden. The proposed 3L-CMV methods significantly reduce harmonic distortion compared to both Two-level CMV (2L-CMV) and Four-level CMV (4L-CMV) SVPWM methods. They exhibit a reduction in peak-to-peak CMV from approximately 40% to 60% and a lower CMV magnitude in the sampling frequency component compared to the 4L-CMV methods. As a result, the proposed system exhibits a considerable reduction in RMS leakage current. Additionally, they can achieve a reduction in switching loss up to 40% in specific conditions, offering improved efficiency compared to continuous PWM schemes.\",\"PeriodicalId\":13079,\"journal\":{\"name\":\"IEEE Access\",\"volume\":\"13 \",\"pages\":\"124962-124978\"},\"PeriodicalIF\":3.4000,\"publicationDate\":\"2025-07-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11082150\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Access\",\"FirstCategoryId\":\"94\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/11082150/\",\"RegionNum\":3,\"RegionCategory\":\"计算机科学\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"COMPUTER SCIENCE, INFORMATION SYSTEMS\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Access","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/11082150/","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, INFORMATION SYSTEMS","Score":null,"Total":0}
Simplified Carrier-Based SVDPWM Methods Using Reduced Common Mode Voltage Vector Redundancy for Improving Output Current Ripple in Four-Level NPC Inverter
In this article, new fast and Three-level reduced common-mode voltage (RCMV) space vector Discontinuous pulse width modulation (SVDPWM) strategies are proposed to achieve high performance in four-level neutral point clamped (4L-NPC) inverters. Redundant reduced common-mode voltage (RCMV) vectors in the space vector diagram (SVD) of the Four-level inverter are utilized to design three discontinuous pulse width modulation (DPWM) control strategies with Three-level CMV (3L-CMV) characteristic, SVDPWM0, SVDPWM1 and HSVDPWM. The last and best one is deduced based on harmonic flux and harmonic distortion factor (HDF) analysis, to improve the output current ripple. For analysis and easy implementation, the SVPWM of the four-level inverter will be solved in the two-level SVD. A simple carrier-based PWM implementation of the RCMV SVDPWM methods will be developed to reduce the computational burden. The proposed 3L-CMV methods significantly reduce harmonic distortion compared to both Two-level CMV (2L-CMV) and Four-level CMV (4L-CMV) SVPWM methods. They exhibit a reduction in peak-to-peak CMV from approximately 40% to 60% and a lower CMV magnitude in the sampling frequency component compared to the 4L-CMV methods. As a result, the proposed system exhibits a considerable reduction in RMS leakage current. Additionally, they can achieve a reduction in switching loss up to 40% in specific conditions, offering improved efficiency compared to continuous PWM schemes.
IEEE AccessCOMPUTER SCIENCE, INFORMATION SYSTEMSENGIN-ENGINEERING, ELECTRICAL & ELECTRONIC
CiteScore
9.80
自引率
7.70%
发文量
6673
审稿时长
6 weeks
期刊介绍:
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