{"title":"用于消费电子产品生理电信号检测的14位250-KS/s免校准SAR ADC","authors":"Yuhua Liang;Ruiwen Liu;Yichen Duan;Zhangming Zhu","doi":"10.1109/TCE.2025.3526687","DOIUrl":null,"url":null,"abstract":"This paper presents a 14-bit 250-KS/s R-C hybrid calibration-free SAR ADC for the detection of physiological electrical signals in consumer electronics. This design adopts a switching scheme to control the resistive DAC (RDAC) and capacitive DAC (CDAC) to avoid the variation of the common-mode voltage. A redundant capacitance is introduced in the CDAC to suppress insufficient signal establishment during inter-stage conversion. The proposed hybrid R-C architecture in this paper can greatly reduce the matching requirement for resistive and capacitive elements while simultaneously addressing the contradiction between the conversion speed and accuracy. With the Nyquist rate input, the post-simulation results show that the effective number of bits (ENOB) is 12.65 bits, the DNL is −0.68/0.8 LSB, and the INL is −1.4/0.84 LSB.","PeriodicalId":13208,"journal":{"name":"IEEE Transactions on Consumer Electronics","volume":"71 1","pages":"1046-1053"},"PeriodicalIF":4.3000,"publicationDate":"2025-01-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 14-Bit 250-KS/s Calibration-Free SAR ADC for the Detection of Physiological Electrical Signals in Consumer Electronics\",\"authors\":\"Yuhua Liang;Ruiwen Liu;Yichen Duan;Zhangming Zhu\",\"doi\":\"10.1109/TCE.2025.3526687\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a 14-bit 250-KS/s R-C hybrid calibration-free SAR ADC for the detection of physiological electrical signals in consumer electronics. This design adopts a switching scheme to control the resistive DAC (RDAC) and capacitive DAC (CDAC) to avoid the variation of the common-mode voltage. A redundant capacitance is introduced in the CDAC to suppress insufficient signal establishment during inter-stage conversion. The proposed hybrid R-C architecture in this paper can greatly reduce the matching requirement for resistive and capacitive elements while simultaneously addressing the contradiction between the conversion speed and accuracy. With the Nyquist rate input, the post-simulation results show that the effective number of bits (ENOB) is 12.65 bits, the DNL is −0.68/0.8 LSB, and the INL is −1.4/0.84 LSB.\",\"PeriodicalId\":13208,\"journal\":{\"name\":\"IEEE Transactions on Consumer Electronics\",\"volume\":\"71 1\",\"pages\":\"1046-1053\"},\"PeriodicalIF\":4.3000,\"publicationDate\":\"2025-01-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Consumer Electronics\",\"FirstCategoryId\":\"94\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10829812/\",\"RegionNum\":2,\"RegionCategory\":\"计算机科学\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q1\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Consumer Electronics","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/10829812/","RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
A 14-Bit 250-KS/s Calibration-Free SAR ADC for the Detection of Physiological Electrical Signals in Consumer Electronics
This paper presents a 14-bit 250-KS/s R-C hybrid calibration-free SAR ADC for the detection of physiological electrical signals in consumer electronics. This design adopts a switching scheme to control the resistive DAC (RDAC) and capacitive DAC (CDAC) to avoid the variation of the common-mode voltage. A redundant capacitance is introduced in the CDAC to suppress insufficient signal establishment during inter-stage conversion. The proposed hybrid R-C architecture in this paper can greatly reduce the matching requirement for resistive and capacitive elements while simultaneously addressing the contradiction between the conversion speed and accuracy. With the Nyquist rate input, the post-simulation results show that the effective number of bits (ENOB) is 12.65 bits, the DNL is −0.68/0.8 LSB, and the INL is −1.4/0.84 LSB.
期刊介绍:
The main focus for the IEEE Transactions on Consumer Electronics is the engineering and research aspects of the theory, design, construction, manufacture or end use of mass market electronics, systems, software and services for consumers.