AlignMalloc:与大规模GPU动态分配的UVM预取对齐的扭曲感知内存重排

IF 5.6 2区 计算机科学 Q1 COMPUTER SCIENCE, THEORY & METHODS
Jiajian Zhang;Fangyu Wu;Hai Jiang;Qiufeng Wang;Genlang Chen;Guangliang Cheng;Eng Gee Lim;Keqin Li
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引用次数: 0

摘要

随着并行计算任务的复杂性和规模的迅速扩大,对高效的GPU动态内存分配的需求变得越来越重要。虽然在为大量应用程序开发动态分配器方面已经取得了进展,但由于低效的内存访问行为,它们的实际适用性仍然受到限制。该文介绍了一种新的内存管理系统AlignMalloc,它与统一虚拟内存(UVM)预取策略保持一致,显著提高了大规模动态分配场景下的内存分配和访问性能。我们分析了UVM访问的基本低效率,并首先揭示了内存访问和UVM预取方法之间的不匹配。为了解决这个问题,AlignMalloc实现了一个感知翘曲的内存重排策略,该策略利用翘曲的规律性来与UVM的静态预取设置保持一致。此外,AlignMalloc在主机共同管理的框架中引入了一个基于OR树的结构,以进一步优化动态分配。综合实验表明,AlignMalloc大大优于当前最先进的系统,在动态分配方面实现了高达2.7倍的改进,在内存访问方面实现了2.3倍的改进。此外,八个具有不同内存访问模式的实际应用程序表现出一致的性能增强,平均速度提高了1.5倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
AlignMalloc: Warp-Aware Memory Rearrangement Aligned With UVM Prefetching for Large-Scale GPU Dynamic Allocations
As parallel computing tasks rapidly expand in both complexity and scale, the need for efficient GPU dynamic memory allocation becomes increasingly important. While progress has been made in developing dynamic allocators for substantial applications, their real-world applicability is still limited due to inefficient memory access behaviors. This paper introduces AlignMalloc, a novel memory management system that aligns with the Unified Virtual Memory (UVM) prefetching strategy, significantly enhancing both memory allocation and access performance in large-scale dynamic allocation scenarios. We analyze the fundamental inefficiencies in UVM access and first reveal the mismatch between memory access and UVM prefetching methods. To resolve this issue, AlignMalloc implements a warp-aware memory rearrangement strategy that exploits the regularity of warps to align with the UVM’s static prefetching setup. Additionally, AlignMalloc introduces an OR tree-based structure within a host-co-managed framework to further optimize dynamic allocation. Comprehensive experiments demonstrate that AlignMalloc substantially outperforms current state-of-the-art systems, achieving up to $2.7 \times$ improvement in dynamic allocation and $2.3 \times$ in memory access. Additionally, eight real-world applications with diverse memory access patterns exhibit consistent performance enhancements, with average speedups $1.5 \times$.
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来源期刊
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems 工程技术-工程:电子与电气
CiteScore
11.00
自引率
9.40%
发文量
281
审稿时长
5.6 months
期刊介绍: IEEE Transactions on Parallel and Distributed Systems (TPDS) is published monthly. It publishes a range of papers, comments on previously published papers, and survey articles that deal with the parallel and distributed systems research areas of current importance to our readers. Particular areas of interest include, but are not limited to: a) Parallel and distributed algorithms, focusing on topics such as: models of computation; numerical, combinatorial, and data-intensive parallel algorithms, scalability of algorithms and data structures for parallel and distributed systems, communication and synchronization protocols, network algorithms, scheduling, and load balancing. b) Applications of parallel and distributed computing, including computational and data-enabled science and engineering, big data applications, parallel crowd sourcing, large-scale social network analysis, management of big data, cloud and grid computing, scientific and biomedical applications, mobile computing, and cyber-physical systems. c) Parallel and distributed architectures, including architectures for instruction-level and thread-level parallelism; design, analysis, implementation, fault resilience and performance measurements of multiple-processor systems; multicore processors, heterogeneous many-core systems; petascale and exascale systems designs; novel big data architectures; special purpose architectures, including graphics processors, signal processors, network processors, media accelerators, and other special purpose processors and accelerators; impact of technology on architecture; network and interconnect architectures; parallel I/O and storage systems; architecture of the memory hierarchy; power-efficient and green computing architectures; dependable architectures; and performance modeling and evaluation. d) Parallel and distributed software, including parallel and multicore programming languages and compilers, runtime systems, operating systems, Internet computing and web services, resource management including green computing, middleware for grids, clouds, and data centers, libraries, performance modeling and evaluation, parallel programming paradigms, and programming environments and tools.
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