CTWR: A congestion, temperature and wear-aware routing algorithm for partially-connected 3D network-on-chip

Three-dimensional Network-on-Chip (3D-NoC) is an efficient solution to overcome communication limitations in complex System-on-Chip (SoC) architectures. However, challenges such as increased temperature, traffic congestion, and link wear-out significantly impact network performance and lifespan. In this study, we propose an adaptive routing algorithm named CTWR (Congestion, Temperature and Wear-aware Routing), which simultaneously considers temperature, congestion, and wear-out while utilizing both intra-layer and inter-layer routing approaches to enhance network performance. The algorithm employs a dynamic approach to assess the real-time status of vertical links to control and reduce wear-out, selecting paths that mitigate thermal hotspots, balance traffic distribution, and extend the lifespan of interconnects. Extensive assessments and simulations performed under diverse traffic scenarios and multiple vertical link or elevator layout configurations indicate that the CTWR algorithm outperforms ETW, EF, HE, and Nezarat routing methods in reducing average packet delay by 92.71 %, 67.84 %, 56.33 %, and 26.91 %, respectively. Furthermore, our proposed approach enhances average network throughput by 9.88 %, 4.38 %, 2.64 %, and 1.66 % compared to these methods. Thermal analysis of the chip surface also reveals a lower overall temperature and a more balanced heat distribution than competing techniques.