FPGA based high speed parallel modular polynomial multiplier for lattice based cryptosystems

More and more Field-Programmable Gate Array (FPGA) devices are being used in Internet-of-Things (IoT) devices and other lightweight applications, which enable the implementation of lattice-based cryptography (LBC) with very low complexity and flexibility. Ring-Learning with Error (R-LWE) problem is based on the promising and effective public key cryptography approach LBC, which allows for more efficient implementation. The most time-consuming operation in R-LWE is polynomial multiplication, which can be accomplished utilizing the Number Theoretic Transform (NTT) and the Schoolbook Polynomial Multiplication (SPM) algorithm. This research paper focused to develop the SPM algorithm for the R-LWE crypto processor using an FPGA-enabled low latency and high-speed parallel modular polynomial multiplier. The proposed modular polynomial multiplier uses systolic architecture to minimize the computational cost of the SPM method. Similarly, the proposed multiplier is expanded to design 4-bit, 16-bit, and 256-bit multiplication using the SPM algorithm, resulting in a low latency and high-speed cryptoprocessor. Finally, the hardware architectures of the R-LWE cryptoprocessor with the proposed multiplier are simulated using Xilinx Verilog coding. The result analysis revealed that the proposed R-LWE cryptoprocessor with the proposed modular polynomial multiplier 256-bit polynomial multiplication achieves 1090.453 MHz maximum frequency, 10,707.93kbps throughput, and 0.10136 delay on the Virtex-7 FPGA platform.