A parallel and pipelined high speed Montgomery modular multiplier for IoT devices

Lightweight authentication of Internet of Things devices requires the efficient implementation of cryptographic Montgomery modular multiplier. However, current Montgomery modular multiplier exhibits limited optimization for data dependencies, resulting in increased idle cycles in the key operation units. In this paper, we propose a parallel and pipelined Montgomery Multiplier (PPMM). The design reduces the overall clock cycle time by leveraging the core unit and planning algorithm scheduling structure with less data dependency. Moreover, we design the multiplier-adder unit with appropriate number of bits and pipeline to improve the overall frequency and give the relevant formulas between clock cycles and radix. Finally, we give an optimized implementation on Xilinx Virtex-7 FPGA over general GF(p) for field sizes 256, 384, and 512 bits. Experiments show that the PPMM takes only $0.123\mu s$, $0.150\mu s$ and $0.190\mu s$ to perform the high-radix modular multiplication of 256, 384 and 512 bits. Compared with other FPGA implementations, our design demonstrates superior performance in terms of speed and throughput. It achieves a higher throughput rate at greater bit counts, making it well-suited for security-intensive applications. Specifically, the 384-bits PPMM with appropriate ATP performance is nearly 2.6 times faster than the reference design.