GPU上高效通信的核外图形处理

IF 5.6 2区 计算机科学 Q1 COMPUTER SCIENCE, THEORY & METHODS
Qiange Wang;Xin Ai;Yongze Yan;Shufeng Gong;Yanfeng Zhang;Jing Chen;Ge Yu
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引用次数: 0

摘要

在内存有限的gpu上进行大规模图形处理的关键性能瓶颈是主机- gpu图形数据传输。现有的gpu加速图形处理框架通过在运行时管理活动子图传输来解决这个问题。一些框架采用基于带有过滤器或压缩的显式内存复制的显式传输管理方法。另一些则采用基于按需访问和零复制机制或统一虚拟内存的隐式传输管理方法。经过深入的分析,我们发现随着活动顶点的演变,两种方法在不同工作负载下的性能会有所不同。由于大量冗余数据传输、高CPU压缩开销或低带宽利用率,采用单一方法通常会导致性能次优。此外,这些方法缺乏有效的缓存管理方法来解决图处理的不规则和稀疏的内存访问模式。在这项工作中,我们提出了一种混合传输管理方法,该方法在运行时吸收了这两种传输方法的优点。此外,我们提出了一个高效的以顶点为中心的图形缓存框架,该框架通过在运行时缓存频繁访问的图形数据来最小化CPU-GPU通信。基于这些技术,我们提出了HytGraph,一个gpu加速的图形处理框架,它通过一组有效的任务调度优化来提高性能。在真实世界和合成图形上的实验表明,与最先进的gpu加速图形处理系统Grus、Subway和EMOGI相比,HytGraph的平均速度分别达到了2.5倍、5.0倍和2.0倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Towards Communication-Efficient Out-of-Core Graph Processing on the GPU
The key performance bottleneck of large-scale graph processing on memory-limited GPUs is the host-GPU graph data transfer. Existing GPU-accelerated graph processing frameworks address this issue by managing the active subgraph transfer at runtime. Some frameworks adopt explicit transfer management approaches based on explicit memory copy with filter or compaction. In contrast, others adopt implicit transfer management approaches based on on-demand accesses with the zero-copy mechanism or unified virtual memory. Having made intensive analysis, we find that as the active vertices evolve, the performance of the two approaches varies in different workloads. Due to heavy redundant data transfers, high CPU compaction overhead, or low bandwidth utilization, adopting a single approach often results in suboptimal performance. Moreover, these methods lack effective cache management methods to address the irregular and sparse memory access pattern of graph processing. In this work, we propose a hybrid transfer management approach that takes the merits of both two transfer approaches at runtime. Moreover, we present an efficient vertex-centric graph caching framework that minimizes CPU-GPU communication by caching frequently accessed graph data at runtime. Based on these techniques, we present HytGraph, a GPU-accelerated graph processing framework, which is empowered by a set of effective task-scheduling optimizations to improve performance. Experiments on real-world and synthetic graphs show that HytGraph achieves average speedups of 2.5 ×, 5.0 ×, and 2.0 × compared to the state-of-the-art GPU-accelerated graph processing systems, Grus, Subway, and EMOGI, respectively.
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来源期刊
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems 工程技术-工程:电子与电气
CiteScore
11.00
自引率
9.40%
发文量
281
审稿时长
5.6 months
期刊介绍: IEEE Transactions on Parallel and Distributed Systems (TPDS) is published monthly. It publishes a range of papers, comments on previously published papers, and survey articles that deal with the parallel and distributed systems research areas of current importance to our readers. Particular areas of interest include, but are not limited to: a) Parallel and distributed algorithms, focusing on topics such as: models of computation; numerical, combinatorial, and data-intensive parallel algorithms, scalability of algorithms and data structures for parallel and distributed systems, communication and synchronization protocols, network algorithms, scheduling, and load balancing. b) Applications of parallel and distributed computing, including computational and data-enabled science and engineering, big data applications, parallel crowd sourcing, large-scale social network analysis, management of big data, cloud and grid computing, scientific and biomedical applications, mobile computing, and cyber-physical systems. c) Parallel and distributed architectures, including architectures for instruction-level and thread-level parallelism; design, analysis, implementation, fault resilience and performance measurements of multiple-processor systems; multicore processors, heterogeneous many-core systems; petascale and exascale systems designs; novel big data architectures; special purpose architectures, including graphics processors, signal processors, network processors, media accelerators, and other special purpose processors and accelerators; impact of technology on architecture; network and interconnect architectures; parallel I/O and storage systems; architecture of the memory hierarchy; power-efficient and green computing architectures; dependable architectures; and performance modeling and evaluation. d) Parallel and distributed software, including parallel and multicore programming languages and compilers, runtime systems, operating systems, Internet computing and web services, resource management including green computing, middleware for grids, clouds, and data centers, libraries, performance modeling and evaluation, parallel programming paradigms, and programming environments and tools.
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