面向擦除编码存储的负载均衡冗余转换

IF 5.6 2区 计算机科学 Q1 COMPUTER SCIENCE, THEORY & METHODS
Keyun Cheng;Huancheng Puyang;Xiaolu Li;Patrick P. C. Lee;Yuchong Hu;Jie Li;Ting-Yi Wu
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引用次数: 0

摘要

冗余转换使擦除编码存储能够通过即时使用新编码参数重新编码数据来适应不同的性能和可靠性要求。现有的研究侧重于带宽驱动的冗余过渡,这种方法降低了各存储节点之间的过渡带宽,但实际冗余过渡性能仍受到负载最重节点的瓶颈制约。我们提出的 BART 是一种负载平衡冗余过渡方案,旨在通过精心安排的并行化缩短冗余过渡时间。我们的研究表明,由于解决方案空间很大,因此很难找到最佳负载平衡解决方案。鉴于这一挑战,BART 将冗余转换问题分解为多个子问题,并通过高效的启发式方法解决这些子问题。我们使用大规模存储模拟和阿里云上的 HDFS 原型实验对 BART 进行了评估。结果表明,与带宽驱动方法相比,BART 能显著缩短冗余转换时间。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Toward Load-Balanced Redundancy Transitioning for Erasure-Coded Storage
Redundancy transitioning enables erasure-coded storage to adapt to varying performance and reliability requirements by re-encoding data with new coding parameters on-the-fly. Existing studies focus on bandwidth-driven redundancy transitioning that reduces the transitioning bandwidth across storage nodes, yet the actual redundancy transitioning performance remains bottlenecked by the most loaded node. We present BART, a load-balanced redundancy transitioning scheme that aims to reduce the redundancy transitioning time via carefully scheduled parallelization. We show that finding an optimal load-balanced solution is difficult due to the large solution space. Given this challenge, BART decomposes the redundancy transitioning problem into multiple sub-problems and solves the sub-problems via efficient heuristics. We evaluate BART using both simulations for large-scale storage and HDFS prototype experiments on Alibaba Cloud. We show that BART significantly reduces the redundancy transitioning time compared with the bandwidth-driven approach.
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来源期刊
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems 工程技术-工程:电子与电气
CiteScore
11.00
自引率
9.40%
发文量
281
审稿时长
5.6 months
期刊介绍: IEEE Transactions on Parallel and Distributed Systems (TPDS) is published monthly. It publishes a range of papers, comments on previously published papers, and survey articles that deal with the parallel and distributed systems research areas of current importance to our readers. Particular areas of interest include, but are not limited to: a) Parallel and distributed algorithms, focusing on topics such as: models of computation; numerical, combinatorial, and data-intensive parallel algorithms, scalability of algorithms and data structures for parallel and distributed systems, communication and synchronization protocols, network algorithms, scheduling, and load balancing. b) Applications of parallel and distributed computing, including computational and data-enabled science and engineering, big data applications, parallel crowd sourcing, large-scale social network analysis, management of big data, cloud and grid computing, scientific and biomedical applications, mobile computing, and cyber-physical systems. c) Parallel and distributed architectures, including architectures for instruction-level and thread-level parallelism; design, analysis, implementation, fault resilience and performance measurements of multiple-processor systems; multicore processors, heterogeneous many-core systems; petascale and exascale systems designs; novel big data architectures; special purpose architectures, including graphics processors, signal processors, network processors, media accelerators, and other special purpose processors and accelerators; impact of technology on architecture; network and interconnect architectures; parallel I/O and storage systems; architecture of the memory hierarchy; power-efficient and green computing architectures; dependable architectures; and performance modeling and evaluation. d) Parallel and distributed software, including parallel and multicore programming languages and compilers, runtime systems, operating systems, Internet computing and web services, resource management including green computing, middleware for grids, clouds, and data centers, libraries, performance modeling and evaluation, parallel programming paradigms, and programming environments and tools.
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