Jiaqi Yu;Wenming Guo;Feng Zhou;Linjin Xie;Mingmin Zhang;Lihua Cao
{"title":"用于三相并网电源变换器的新型离散锁频环路*","authors":"Jiaqi Yu;Wenming Guo;Feng Zhou;Linjin Xie;Mingmin Zhang;Lihua Cao","doi":"10.23919/CJEE.2025.000114","DOIUrl":null,"url":null,"abstract":"A novel discrete-time frequency-locked loop (FLL) for three-phase grid-connected power converters that features rapid dynamic response and low computational cost is introduced. Firstly, a simplified nonlinear frequency-estimation model that leverages the inherent orthogonality of voltage signals in the <tex>$a$</tex>β- frame, along with an optimal fixed-length delay, is proposed. Subsequently, a discrete-time FLL structure is developed based on this model. In addition, a convergence analysis and parameter design are presented. Finally, a comparative experiment with established methods is conducted, and the results demonstrate that the proposed FLL offers a faster dynamic response, requires fewer parameters to be tuned, ensures a smoother startup process, and maintains a relatively lower computational cost.","PeriodicalId":36428,"journal":{"name":"Chinese Journal of Electrical Engineering","volume":"11 1","pages":"174-183"},"PeriodicalIF":0.0000,"publicationDate":"2025-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10955299","citationCount":"0","resultStr":"{\"title\":\"Novel Discrete-time Frequency-locked Loop for Three-phase Grid-connected Power Converters*\",\"authors\":\"Jiaqi Yu;Wenming Guo;Feng Zhou;Linjin Xie;Mingmin Zhang;Lihua Cao\",\"doi\":\"10.23919/CJEE.2025.000114\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel discrete-time frequency-locked loop (FLL) for three-phase grid-connected power converters that features rapid dynamic response and low computational cost is introduced. Firstly, a simplified nonlinear frequency-estimation model that leverages the inherent orthogonality of voltage signals in the <tex>$a$</tex>β- frame, along with an optimal fixed-length delay, is proposed. Subsequently, a discrete-time FLL structure is developed based on this model. In addition, a convergence analysis and parameter design are presented. Finally, a comparative experiment with established methods is conducted, and the results demonstrate that the proposed FLL offers a faster dynamic response, requires fewer parameters to be tuned, ensures a smoother startup process, and maintains a relatively lower computational cost.\",\"PeriodicalId\":36428,\"journal\":{\"name\":\"Chinese Journal of Electrical Engineering\",\"volume\":\"11 1\",\"pages\":\"174-183\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2025-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10955299\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Chinese Journal of Electrical Engineering\",\"FirstCategoryId\":\"1087\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10955299/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q1\",\"JCRName\":\"Engineering\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Chinese Journal of Electrical Engineering","FirstCategoryId":"1087","ListUrlMain":"https://ieeexplore.ieee.org/document/10955299/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"Engineering","Score":null,"Total":0}
Novel Discrete-time Frequency-locked Loop for Three-phase Grid-connected Power Converters*
A novel discrete-time frequency-locked loop (FLL) for three-phase grid-connected power converters that features rapid dynamic response and low computational cost is introduced. Firstly, a simplified nonlinear frequency-estimation model that leverages the inherent orthogonality of voltage signals in the $a$β- frame, along with an optimal fixed-length delay, is proposed. Subsequently, a discrete-time FLL structure is developed based on this model. In addition, a convergence analysis and parameter design are presented. Finally, a comparative experiment with established methods is conducted, and the results demonstrate that the proposed FLL offers a faster dynamic response, requires fewer parameters to be tuned, ensures a smoother startup process, and maintains a relatively lower computational cost.