An Efficient QC-LDPC channel encoder/decoder architecture with parallel vector-matrix computations for 5G wireless networks on FPGA

The Consultative Committee for Space Data Systems (CCSDS) has selected quasi-cyclic low-density parity-check (QC-LDPC) codes to enhance error correction performance in diverse wireless communication systems. The growing use of QC-LDPC codes necessitates a low-latency and low-complexity encoder/decoder architecture that may be implemented in practical baseband chips. However, the storage of information bit widths with multiple expansion factors would deteriorate the encoder's throughput and adaptability in a QC-LDPC encoding process. In order to compress the expansion factors and improve the encoder's reconfiguration capability by minimizing the information bits width, a Field Programmable Gate Array (FPGA) enabled QC-LDPC encoder with an information bits reordering mechanism (IBRM) is developed in this study. Additionally, the complexity of calculating the parity check matrix (PCM) is reduced by utilizing the parallel vector-matrix computations (PVMC) method. The decoding process is then carried out by a new logarithmic likelihood-ratio (LLR) tagging method-enabled decoder architecture, which reduces the computational complexity of the suggested decoder architecture. Furthermore, the basic addition and subtraction operations are carried out by a reconfigurable unified adder and subtractor unit (RUAS) that reduces the overall complexity of the decoder architecture. Finally, using Xilinx Verilog coding and Matlab, the VLSI architectures of the proposed encoder/decoder are implemented in FPGA. The analysis of the results shows that the proposed encoder architecture achieves a throughput of 11.974 Gbps and a clock frequency (CF) of 455 .913MHz. Likewise, the decoder consumes 0.002193 $\left(\mu s\right)$ latency to complete the decoding process.