FPGA Integrated Distributed Homogenous Clustered AODV Routing Analysis for Mobile Ad Hoc Networks

The research letter focuses on the hardware chip design of the Distributed Homogenous Clustered Ad hoc On-Demand Distance Vector (DHMC-AODV) routing protocol for MANETs. Distributed clustering has been used for the homogenous clustered routing formation that reduces the complex computational processing time and supports parallel computing in a multilevel clustering environment. The novelty of the work is that the hardware routing chip is verified in an FPGA-integrated environment with a scalable network design. The routed chip performance is determined based on parallel processing-enabled FPGA hardware indices such as IoBs, slices, and LUTs for the network configuration (N = 64). The performance improvement of the proposed protocol is claimed on ZedBoard FPGA, compared with the existing protocols in terms of power, E2ED, and overhead is 9.2%, 5.1% to 10.2%, 11.5% to 12.4%, and 14.3% to 16.1% respectively. The PDR is approximately 1.0 for all the protocols when the network is fully accessible.