Hardware Accelerator for a Power Efficient Single-lead Dry-electrode ECG Wearable Design.

Single-lead electrocardiographic (ECG) monitoring wearables are becoming candidate technologies for long-term remote monitoring applications. Current wearable disadvantages include high power consumption from computational complex pre-processing leading to low battery life. A hardware (HW) architecture for dry electrode-based ECG signal processing to increase wearable longevity is proposed. The technology is based off an analog-front end (AFE) chip combined with a field programmable gated arrays (FPGA)-based optimized cubic Hermite interpolation approach for signal processing. This system is deployed on a FPGA board featuring a single-core processor. The architecture uses 0.01 W, utilizes 0.67% and 0.44% of available look-up-tables (LUTs) and flip-flops (FFs) components on FPGA and performed real-time signal processing. Signal quality indexes (SQIs) and signal to noise ratios (SNR) information are computed where the HW processed signals showed an average SNR of 16.4 dB. ECG R-peaks are visually identified, making this architecture suitable for heart rate (HR), and heart rate variability (HRV) estimations in long-term dry-electrode single-lead ECG monitoring applications.