Self-heating optimisation of nanosheet field effect transistor performance with physics-based calibrated simulation setup

One of the best ways to scale down below sub-7 nm technology nodes seems to be to use vertically stacked horizontal nanosheet gates all around the transistors. To analyse transistor structure and improve the performance of the device, in this work, we compare the physical models, geometrical configuration and electrical performance of the vertically stacked horizontal nanosheet transistors. We investigate how the gate-length, gate oxide thickness, work function engineering, nanosheets – their width, height, number of stacked sheets with doping concentration, gate materials can affect the electrical performance and here we present the suitable design required for vertically stacked nanosheet field effect transistors (FETs) for improved performance using TCAD calibration. Also, the self-heating effect is analysed by varying the number of nanosheets, width of nanosheets using a thermodynamic model. The calibration set-up exhibits good efficiency towards the technology node. The significant device variability might result from the stacked nanosheet architectures becoming more complicated over the adverse device improvement.