Cai Kong;Weiwei Huan;Jian Wang;Dali Li;Hui Sun;Xuehong Zhang;Fenghua Ye;Kaizhi Lin
{"title":"面向高性能计算的垂直电源传输架构","authors":"Cai Kong;Weiwei Huan;Jian Wang;Dali Li;Hui Sun;Xuehong Zhang;Fenghua Ye;Kaizhi Lin","doi":"10.1109/TPEL.2025.3531414","DOIUrl":null,"url":null,"abstract":"Power delivery is becoming especially critical for high-performance computing system. This article realizes a novel vertical power delivery (VPD) architecture with high delivery efficiency and system computing performance. A 12–1.83 V voltage regulator (VR) board is built via blind/buried via process. Based on compatible design of VR board and mainboard, this VR board has been directly assembled with a server mainboard to form a computing system. Static output and transient response tests indicate superior stability of VPD prototype. Peak and full load efficiencies of prototype are confirmed to be 93.0% and 91.5%, respectively, better than lateral power delivery (LPD) and previous reports. This VPD design also enables direct power supply to central processing unit. Therefore, system computing performances have been further investigated to evaluate application of built VPD in real server environment, and benchmark score of VPD system is acquired to be 15 538, higher than LPD server (14 599). The superior performances can be attributed to reduced power distribution network resistance, revealed by path resistance (<italic>R</i><sub>path</sub>) simulation. At last, we have extended the manufacture process of VR board into mainboard, facilitating direct assembly of power converter on back side of server mainboard. The built VPD realizes scalable efficiencies.","PeriodicalId":13267,"journal":{"name":"IEEE Transactions on Power Electronics","volume":"40 5","pages":"6663-6674"},"PeriodicalIF":6.5000,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Vertical Power Delivery Architecture for High-Performance Computing\",\"authors\":\"Cai Kong;Weiwei Huan;Jian Wang;Dali Li;Hui Sun;Xuehong Zhang;Fenghua Ye;Kaizhi Lin\",\"doi\":\"10.1109/TPEL.2025.3531414\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Power delivery is becoming especially critical for high-performance computing system. This article realizes a novel vertical power delivery (VPD) architecture with high delivery efficiency and system computing performance. A 12–1.83 V voltage regulator (VR) board is built via blind/buried via process. Based on compatible design of VR board and mainboard, this VR board has been directly assembled with a server mainboard to form a computing system. Static output and transient response tests indicate superior stability of VPD prototype. Peak and full load efficiencies of prototype are confirmed to be 93.0% and 91.5%, respectively, better than lateral power delivery (LPD) and previous reports. This VPD design also enables direct power supply to central processing unit. Therefore, system computing performances have been further investigated to evaluate application of built VPD in real server environment, and benchmark score of VPD system is acquired to be 15 538, higher than LPD server (14 599). The superior performances can be attributed to reduced power distribution network resistance, revealed by path resistance (<italic>R</i><sub>path</sub>) simulation. At last, we have extended the manufacture process of VR board into mainboard, facilitating direct assembly of power converter on back side of server mainboard. The built VPD realizes scalable efficiencies.\",\"PeriodicalId\":13267,\"journal\":{\"name\":\"IEEE Transactions on Power Electronics\",\"volume\":\"40 5\",\"pages\":\"6663-6674\"},\"PeriodicalIF\":6.5000,\"publicationDate\":\"2025-01-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Power Electronics\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10848125/\",\"RegionNum\":1,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q1\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Power Electronics","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10848125/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
A Vertical Power Delivery Architecture for High-Performance Computing
Power delivery is becoming especially critical for high-performance computing system. This article realizes a novel vertical power delivery (VPD) architecture with high delivery efficiency and system computing performance. A 12–1.83 V voltage regulator (VR) board is built via blind/buried via process. Based on compatible design of VR board and mainboard, this VR board has been directly assembled with a server mainboard to form a computing system. Static output and transient response tests indicate superior stability of VPD prototype. Peak and full load efficiencies of prototype are confirmed to be 93.0% and 91.5%, respectively, better than lateral power delivery (LPD) and previous reports. This VPD design also enables direct power supply to central processing unit. Therefore, system computing performances have been further investigated to evaluate application of built VPD in real server environment, and benchmark score of VPD system is acquired to be 15 538, higher than LPD server (14 599). The superior performances can be attributed to reduced power distribution network resistance, revealed by path resistance (Rpath) simulation. At last, we have extended the manufacture process of VR board into mainboard, facilitating direct assembly of power converter on back side of server mainboard. The built VPD realizes scalable efficiencies.
期刊介绍:
The IEEE Transactions on Power Electronics journal covers all issues of widespread or generic interest to engineers who work in the field of power electronics. The Journal editors will enforce standards and a review policy equivalent to the IEEE Transactions, and only papers of high technical quality will be accepted. Papers which treat new and novel device, circuit or system issues which are of generic interest to power electronics engineers are published. Papers which are not within the scope of this Journal will be forwarded to the appropriate IEEE Journal or Transactions editors. Examples of papers which would be more appropriately published in other Journals or Transactions include: 1) Papers describing semiconductor or electron device physics. These papers would be more appropriate for the IEEE Transactions on Electron Devices. 2) Papers describing applications in specific areas: e.g., industry, instrumentation, utility power systems, aerospace, industrial electronics, etc. These papers would be more appropriate for the Transactions of the Society which is concerned with these applications. 3) Papers describing magnetic materials and magnetic device physics. These papers would be more appropriate for the IEEE Transactions on Magnetics. 4) Papers on machine theory. These papers would be more appropriate for the IEEE Transactions on Power Systems. While original papers of significant technical content will comprise the major portion of the Journal, tutorial papers and papers of historical value are also reviewed for publication.