Exploring the potential of FinFET transistor technology in reconfigurable logic gates for enhanced computing performance

Advanced logic gates and transistor technologies play a crucial role in the design of high-speed computing systems. In this paper, a novel 3-dimensional fin-shaped reconfigurable transistor is presented, which exhibits identical behavior in both n-enhancement mode and p-enhancement mode operations. The key highlight of this reconfigurable transistor lies in its ability to integrate XNOR, NOT, and AND gates within a single device. Unlike conventional reconfigurable transistors, the proposed device incorporates a dual-doped n⁺/p⁺ source and a Schottky drain region. Notably, this device only requires a control gate, while the drain electrode serves the dual purpose of being the output and program gate. The findings demonstrate remarkable performance characteristics for the n-enhancement mode and p-enhancement mode operations. Specifically, the on-state current is measured to be 3.68 µA and 2.85 µA, with corresponding on/off current ratios of 11.25 × 10⁸ and 1.23 × 10⁸, respectively. Moreover, the device achieves a subthreshold swing of 61 mV/dec and 63 mV/dec for the n-enhancement mode and p-enhancement mode, respectively. This innovative design highlights the potential of utilizing a single FinFET reconfigurable transistor to design complex logic gates, demonstrating a significant advancement in integrated circuit technology towards enhanced efficiency and versatility.