Sebastian Brandhofer, Ilia Polian, Stefanie Barz, Daniel Bhatti
{"title":"在近端量子计算机上以硬件高效方式制备图状态","authors":"Sebastian Brandhofer, Ilia Polian, Stefanie Barz, Daniel Bhatti","doi":"arxiv-2409.10807","DOIUrl":null,"url":null,"abstract":"Highly entangled quantum states are an ingredient in numerous applications in\nquantum computing. However, preparing these highly entangled quantum states on\ncurrently available quantum computers at high fidelity is limited by ubiquitous\nerrors. Besides improving the underlying technology of a quantum computer, the\nscale and fidelity of these entangled states in near-term quantum computers can\nbe improved by specialized compilation methods. In this work, the compilation\nof quantum circuits for the preparation of highly entangled\narchitecture-specific graph states is addressed by defining and solving a\nformal model. Our model incorporates information about gate cancellations, gate\ncommutations, and accurate gate timing to determine an optimized graph state\npreparation circuit. Up to now, these aspects have only been considered\nindependently of each other, typically applied to arbitrary quantum circuits.\nWe quantify the quality of a generated state by performing stabilizer\nmeasurements and determining its fidelity. We show that our new method reduces\nthe error when preparing a seven-qubit graph state by 3.5x on average compared\nto the state-of-the-art Qiskit solution. For a linear eight-qubit graph state,\nthe error is reduced by 6.4x on average. The presented results highlight the\nability of our approach to prepare higher fidelity or larger-scale graph states\non gate-based quantum computing hardware.","PeriodicalId":501226,"journal":{"name":"arXiv - PHYS - Quantum Physics","volume":"16 1","pages":""},"PeriodicalIF":0.0000,"publicationDate":"2024-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Hardware-Efficient Preparation of Graph States on Near-Term Quantum Computers\",\"authors\":\"Sebastian Brandhofer, Ilia Polian, Stefanie Barz, Daniel Bhatti\",\"doi\":\"arxiv-2409.10807\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Highly entangled quantum states are an ingredient in numerous applications in\\nquantum computing. However, preparing these highly entangled quantum states on\\ncurrently available quantum computers at high fidelity is limited by ubiquitous\\nerrors. Besides improving the underlying technology of a quantum computer, the\\nscale and fidelity of these entangled states in near-term quantum computers can\\nbe improved by specialized compilation methods. In this work, the compilation\\nof quantum circuits for the preparation of highly entangled\\narchitecture-specific graph states is addressed by defining and solving a\\nformal model. Our model incorporates information about gate cancellations, gate\\ncommutations, and accurate gate timing to determine an optimized graph state\\npreparation circuit. Up to now, these aspects have only been considered\\nindependently of each other, typically applied to arbitrary quantum circuits.\\nWe quantify the quality of a generated state by performing stabilizer\\nmeasurements and determining its fidelity. We show that our new method reduces\\nthe error when preparing a seven-qubit graph state by 3.5x on average compared\\nto the state-of-the-art Qiskit solution. For a linear eight-qubit graph state,\\nthe error is reduced by 6.4x on average. The presented results highlight the\\nability of our approach to prepare higher fidelity or larger-scale graph states\\non gate-based quantum computing hardware.\",\"PeriodicalId\":501226,\"journal\":{\"name\":\"arXiv - PHYS - Quantum Physics\",\"volume\":\"16 1\",\"pages\":\"\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2024-09-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"arXiv - PHYS - Quantum Physics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/arxiv-2409.10807\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"arXiv - PHYS - Quantum Physics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/arxiv-2409.10807","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Hardware-Efficient Preparation of Graph States on Near-Term Quantum Computers
Highly entangled quantum states are an ingredient in numerous applications in
quantum computing. However, preparing these highly entangled quantum states on
currently available quantum computers at high fidelity is limited by ubiquitous
errors. Besides improving the underlying technology of a quantum computer, the
scale and fidelity of these entangled states in near-term quantum computers can
be improved by specialized compilation methods. In this work, the compilation
of quantum circuits for the preparation of highly entangled
architecture-specific graph states is addressed by defining and solving a
formal model. Our model incorporates information about gate cancellations, gate
commutations, and accurate gate timing to determine an optimized graph state
preparation circuit. Up to now, these aspects have only been considered
independently of each other, typically applied to arbitrary quantum circuits.
We quantify the quality of a generated state by performing stabilizer
measurements and determining its fidelity. We show that our new method reduces
the error when preparing a seven-qubit graph state by 3.5x on average compared
to the state-of-the-art Qiskit solution. For a linear eight-qubit graph state,
the error is reduced by 6.4x on average. The presented results highlight the
ability of our approach to prepare higher fidelity or larger-scale graph states
on gate-based quantum computing hardware.