Changseob Lee, Ikhyeon Kwon, Anirban Samanta, Siwei Li, S. J. Ben Yoo
{"title":"在硅光子 CMOS 平台上采用 P+/P/N/P/N/N+ 掺杂曲线的高性能三端晶闸管 RAM","authors":"Changseob Lee, Ikhyeon Kwon, Anirban Samanta, Siwei Li, S. J. Ben Yoo","doi":"arxiv-2409.07598","DOIUrl":null,"url":null,"abstract":"3T TRAM with doping profile (P+PNPNN+) is experimentally demonstrated on a\nsilicon photonic platform. By using additional implant layers, this device\nprovides excellent memory performance compared to the conventional structure\n(PNPN). TCAD is used to reflect the physical behavior, and the high-speed\nmemory operations are described through the model.","PeriodicalId":501175,"journal":{"name":"arXiv - EE - Systems and Control","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"High Performance Three-Terminal Thyristor RAM with a P+/P/N/P/N/N+ Doping Profile on a Silicon-Photonic CMOS Platform\",\"authors\":\"Changseob Lee, Ikhyeon Kwon, Anirban Samanta, Siwei Li, S. J. Ben Yoo\",\"doi\":\"arxiv-2409.07598\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"3T TRAM with doping profile (P+PNPNN+) is experimentally demonstrated on a\\nsilicon photonic platform. By using additional implant layers, this device\\nprovides excellent memory performance compared to the conventional structure\\n(PNPN). TCAD is used to reflect the physical behavior, and the high-speed\\nmemory operations are described through the model.\",\"PeriodicalId\":501175,\"journal\":{\"name\":\"arXiv - EE - Systems and Control\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2024-09-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"arXiv - EE - Systems and Control\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/arxiv-2409.07598\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"arXiv - EE - Systems and Control","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/arxiv-2409.07598","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High Performance Three-Terminal Thyristor RAM with a P+/P/N/P/N/N+ Doping Profile on a Silicon-Photonic CMOS Platform
3T TRAM with doping profile (P+PNPNN+) is experimentally demonstrated on a
silicon photonic platform. By using additional implant layers, this device
provides excellent memory performance compared to the conventional structure
(PNPN). TCAD is used to reflect the physical behavior, and the high-speed
memory operations are described through the model.