基于保持器的超高速低功耗全加法器的新颖和电压弹性设计

IF 1.8 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Uma Sharma, Mansi Jhamb
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引用次数: 0

摘要

这篇研究文章介绍了一种利用接地保持器电路的创新型 1 位全加法器设计。为了实现全加法器,采用了基于保持器的 XOR-XNOR 单元设计方法。实现全摆幅输出电压是设计全加法器的关键挑战之一。本文提出了 8-T XOR-XNOR 单元,并使用 HSPICE 软件在 90 纳米技术节点上进行了仿真。本研究的主要重点是引入可减少传播延迟并提供全输出电压摆幅的保持器电路。此外,这项研究还提出了基于保持器的超高速低功耗 1 位全加法器(UHSLPFA)的电压弹性原创设计。我们的研究对各种全加法器设计进行了全面比较,重点关注功率耗散 (PWR)、传播延迟 (tp) 和功率延迟积 (PDP)。值得注意的是,与现有同类设计相比,我们提出的 20-T 全加法器设计显著降低了传播延迟和功耗。这种具有电压弹性的超高速、低功耗、基于保持器的 1 位全加法器的应用范围可扩展到算术逻辑单元、乘法器、计算器和图形处理单元的开发。为了评估 UHSLPFA 的电压适应能力,我们在 0.6 至 1.5 V 的电源电压范围内对其进行了仿真。这一评估揭示了 PWR、tp 和 PDP 的变化,展示了我们的设计与当代最先进的替代方案相比所具有的卓越弹性。此外,还在 4 位纹波携带加法器中评估了拟议全加法器的性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

A Novel and Voltage Resilient Design of Ultra-High-Speed Low Power Keeper Based Full Adder

A Novel and Voltage Resilient Design of Ultra-High-Speed Low Power Keeper Based Full Adder

This research article introduces an innovative 1-bit full adder design, leveraging grounded keeper circuitry. To implement full adder, keeper based XOR-XNOR cell -based design approach is used. Achieving full swing output voltage is one of the critical challenges in the designing of full adder. In this paper 8-T XOR-XNOR cell is proposed and simulated using HSPICE software at 90 nm technology node. The introduction of keeper circuit, which decreases propagation delay and offer full output voltage swing, is the primary focus of this research. Furthermore, this work puts forth an original design for a voltage-resilient ultra high-speed low-power keeper-based 1-bit full adder (UHSLPFA). Our research delves into a comprehensive comparison of various full adder designs, focusing on power dissipation (PWR), propagation delay (tp), and power-delay product (PDP). Notably, our proposed 20-T full adder design boasts notably reduced propagation delay and power consumption when compared to the existing counterparts. The envisioned application scope for this voltage-resilient ultra-high-speed-low-power keeper-based 1-bit full adder extends to the development of arithmetic logic units, multipliers, calculators, and graphical processing units. To gauge its voltage resilience, our proposed UHSLPFA is subjected to simulation across a range of supply voltages, from 0.6 to 1.5 V. This evaluation uncovers variations in PWR, tp, and PDP, showcasing the superior resilience of our design compared to contemporary state-of-the-art alternatives. The performance of the proposed full adder is also evaluated in 4-bit ripple carry adder.

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来源期刊
Circuits, Systems and Signal Processing
Circuits, Systems and Signal Processing 工程技术-工程:电子与电气
CiteScore
4.80
自引率
13.00%
发文量
321
审稿时长
4.6 months
期刊介绍: Rapid developments in the analog and digital processing of signals for communication, control, and computer systems have made the theory of electrical circuits and signal processing a burgeoning area of research and design. The aim of Circuits, Systems, and Signal Processing (CSSP) is to help meet the needs of outlets for significant research papers and state-of-the-art review articles in the area. The scope of the journal is broad, ranging from mathematical foundations to practical engineering design. It encompasses, but is not limited to, such topics as linear and nonlinear networks, distributed circuits and systems, multi-dimensional signals and systems, analog filters and signal processing, digital filters and signal processing, statistical signal processing, multimedia, computer aided design, graph theory, neural systems, communication circuits and systems, and VLSI signal processing. The Editorial Board is international, and papers are welcome from throughout the world. The journal is devoted primarily to research papers, but survey, expository, and tutorial papers are also published. Circuits, Systems, and Signal Processing (CSSP) is published twelve times annually.
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