Flexible and High-Efficiency LDPC Encoder Architecture for CCSDS Standard

The Consultative Committee for Space Data Systems (CCSDS) has adopted quasi-cyclic low-density parity-check (QC-LDPC) codes for use in near-Earth (C2) and deep space (AR4JA) communications. Existing encoder architectures for C2 codes, however, fall short in efficiency for high-throughput applications. This paper introduces a comprehensive approach combining algorithmic and architectural optimizations to enhance hardware usage efficiency (HUE) while offering flexibility. We propose an integrated inter-block and intra-block parallel (IIB-IBP) encoding algorithm that leverages the unique matrix structure to significantly enhance performance. Additionally, a matrix-specific command register pretreatment (MSCRP) technique is developed to effectively handle the special dimensions of the generator matrix. Furthermore, we detail an offline design process for the automated generation of the encoder core’s HDL description, facilitating fine-tuning of encoding parallelism, latency, FPGA resource utilization, and overall throughput. Hardware implementation on a Virtex XC5VLX110T FPGA demonstrates that our encoder reaches an impressive throughput of 10.6 Gb/s with only 2531 LUTs and 1040 FFs, achieving a HUE of 2.97 Mbps/logic unit. This performance marks a 70.6% increase in HUE when compared to state-of-the-art designs.