研究面向低功耗和高性能计算的 20T 混合全加法器设计

IF 1.3 4区计算机科学 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

IETE Journal of Research Pub Date : 2024-08-07 DOI:10.1080/03772063.2024.2387292

Satvik Goel, Saurabh Kumar, Ritam Tripathi, Shivansh Bajpai, Rahul Soni, R.K. Chauhan

引用次数: 0

摘要

1 位全加法器是数字电路中的重要构件，广泛应用于算术电路、数字滤波器和计算机存储器等各种应用中。在这项研究中，一个穿透式全加法器被设计成可用于计算全加法器的...

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Investigating the 20T Hybrid Full Adder Design for Low Power and High-Performance Computing

The 1-bit full adder is a crucial building block in digital circuits, widely used in various applications such as arithmetic circuits, digital filters, and computer memory. In this study, a thoroug...

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来源期刊

IETE Journal of Research 工程技术-电信学

CiteScore

3.30

自引率

6.70%

发文量

308

期刊介绍： IETE Journal of Research is a Bimonthly journal published by the Institution of Electronics and Telecommunication Engineers (IETE), India. It publishes scientific and technical papers describing original research work or novel product/process development. Occasionally special issues are brought out on new and emerging research areas. IETE Journal of Research is useful to researchers, engineers, scientists, teachers, managers and students who are interested in keeping a track of original research and development work being carried out in the broad area of electronics, telecommunications, computer science and engineering and information technology.