通过 Tseitin-Awareness 修剪布尔 d-DNNF 电路

Vincent Derkinderen
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引用次数: 0

摘要

d-DNNF形式的布尔电路可以实现可控的概率推理。然而,作为这项工作的一个关键见解,我们表明,常用的d-DNNF编译方法会引入无关的子电路。我们将这些子电路称为 Tseitin 人工制品,因为它们是由于 Tseitintransformation 步骤而引入的--该步骤是将任何电路转换为若干 d-DNNF 知识编译器所需的 CNF 格式的既定程序。我们讨论了如何检测并移除 Tseitin 变量和 Tseitin 伪影,从而实现更简洁的电路。我们根据经验观察到,在同时移除 Tseitin 变量和假象时,电路的平均大小减少了 77.5%。对 Tseitin 伪变量的额外剪枝平均减少了 22.2%。这显著改善了受益于更简洁电路的下游任务,例如概率推理任务。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Pruning Boolean d-DNNF Circuits Through Tseitin-Awareness
Boolean circuits in d-DNNF form enable tractable probabilistic inference. However, as a key insight of this work, we show that commonly used d-DNNF compilation approaches introduce irrelevant subcircuits. We call these subcircuits Tseitin artifacts, as they are introduced due to the Tseitin transformation step -- a well-established procedure to transform any circuit into the CNF format required by several d-DNNF knowledge compilers. We discuss how to detect and remove both Tseitin variables and Tseitin artifacts, leading to more succinct circuits. We empirically observe an average size reduction of 77.5% when removing both Tseitin variables and artifacts. The additional pruning of Tseitin artifacts reduces the size by 22.2% on average. This significantly improves downstream tasks that benefit from a more succinct circuit, e.g., probabilistic inference tasks.
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