A mini I2C bus interface circuit design and its VLSI implementation

The existing I²C interfaces require significant CPU intervention for data communication. In SOC systems, when using internally integrated I²C modules as masters, software control of I/O ports is necessary to emulate the I²C protocol for data transmission. This paper proposes a Mini I²C bus interface circuit design scheme that supports both master and slave modes. The I²C interface features minimal CPU intervention during data transmission, ease of use, small circuit area, and low power consumption. Additionally, the internal state machine design employs independent finite state machines (FSMs) for master and slave modes, enabling flexible configuration of the I²C module to operate in either mode. In comparison to reference (ShenZhen in Microelectronics Technology CO.BJ8M306A, Datasheet.2019.12.2., 2019), the proposed I²C solution reduces CPU instructions by 50% during data transmission, and by 33% compared to reference (GigaDevice Semiconductor Inc. GD32F1x0, Datasheet, 2022). After DC synthesis, the proposed design occupies only 14% of the area and consumes only 3.6% of the power of the Open Source I²C Design (Forencich in verilog-i2c. GitHub repository. Retrieved from https://github.com/alexforencich/verilog-i2c, n.d.). Therefore, this design scheme is better suited for low-power systems. The proposed design was validated through simulation using Xilinx ISE 14.7 with a SPARTAN 3 FPGA model xc3s500e-5pq208, and finally implemented using Huahong 95 nm CMOS technology, demonstrating high integration and low power consumption.