Adaptive PUF design to authenticate and evaluate heterogeneous IPs in edge computing

Edge computing has become quintessential in commercial, healthcare, and industrial applications. It enables real-time data processing at the edge device, thus reducing the data traffic to the cloud and increasing the processing time efficiency. As an edge device, modern System-on-Chips (SoCs) provide scalability, security, and development in an integrated platform. Intellectual Property (IP) core reuse is a boon in SoCs that bridges the gap between integrated circuit design and fabrication. Such edge devices modeled by vendors are bound to ensure high security to avoid piracy. The proposed architecture provides a two-step authentication utilizing a Finite State Machine (FSM) with a secured key obtained from the newly structured Physical Unclonable Function (PUF) within the same edge device, with the primary goal of verifying several heterogeneous IPs to achieve the least power and energy. Two PUF designs, Anderson Arbiter PUF (AA-PUF) and Balanced AA-PUF, have been proposed for two different placements taking advantage of SoC-based architecture. The PUF characteristics have been experimentally validated with and without majority voting and demonstrate their proximity close to the desired value in ZedBoard. The proposed design is a strong PUF with less than 15% area overhead and power dissipation of 1.982 W for a 64-bit response. The experimental validation has evaluated that the power and energy consumptions are 2.56 W and 2.17 J for 52 heterogeneous IPs.