MAB-BMC:同时利用多个 BMC 引擎的形式化验证增强器

IF 2.2 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Devleena Ghosh, Sumana Ghosh, Ansuman Banerjee, R. Gajavelly, Sudhakar Surendran
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引用次数: 0

摘要

近来,有界模型检查(BMC)引擎在形式验证中得到了广泛应用。目前存在不同的 BMC 引擎,它们在优化、表示和求解机制方面各不相同,用于表示和引导待验证设计的底层状态转换。本文的目的是研究 BMC 引擎的组合是否有助于结合它们的优势。我们提出了一种方法,可以创建 BMC 引擎的排序,从而在形式验证中达到更好的深度,而不是在指定时间内单独执行这些引擎。我们的方法使用机器学习,特别是强化学习的多臂匪徒范式,来预测底层电路设计的给定展开深度下性能最佳的 BMC 引擎。我们在硬件模型检查竞赛(HWMCC)基准中的一组基准设计上评估了我们的方法,结果表明,就达到的深度或推导出属性违反所需的时间而言,我们的方法优于最先进的 BMC 引擎。在 80% 以上的情况下,合成的 BMC 引擎序列达到的深度优于 HWMCC 结果和最先进的 super_deep 技术。在 92% 以上在给定时间内未发现违反属性的情况下,它的性能也优于单引擎运行。对于在给定持续时间内发现属性违规的设计,合成序列在所有设计中发现属性违规的时间均少于 HWMCC,并且在 87% 以上的设计中,合成序列的性能优于 super_deep 和单引擎运行。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
MAB-BMC: A Formal Verification Enhancer by Harnessing Multiple BMC Engines Together
In recent times, Bounded Model Checking (BMC) engines have gained wide prominence in formal verification. Different BMC engines exist, differing in their optimization, representations and solving mechanisms used to represent and navigate the underlying state transition of the given design to be verified. The objective of this paper is to examine if combinations of BMC engines can help to combine their strengths. We propose an approach that can create a sequencing of BMC engines that can reach better depth in formal verification, as opposed to executing them alone for a specified time. Our approach uses machine learning, specifically, the Multi-Armed Bandit paradigm of reinforcement learning, to predict the best-performing BMC engine for a given unrolling depth of the underlying circuit design. We evaluate our approach on a set of benchmark designs from the Hardware Model Checking Competition (HWMCC) benchmarks and show that it outperforms the state-of-the-art BMC engines in terms of the depth reached or time taken to deduce a property violation. The synthesized BMC engine sequences reach better depths than HWMCC results and the state-of-the-art technique, super_deep, for more than 80% of the cases. It also outperforms single engine runs for more than 92% of the cases where a property violation is not found within a given time duration. For designs where property violations are found within the given time duration, the synthesized sequences found the property violation in a lesser time than HWMCC for all the designs and outperformed both super_deep and single engine runs for more than 87% of the designs.
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来源期刊
ACM Transactions on Design Automation of Electronic Systems
ACM Transactions on Design Automation of Electronic Systems 工程技术-计算机:软件工程
CiteScore
3.20
自引率
7.10%
发文量
105
审稿时长
3 months
期刊介绍: TODAES is a premier ACM journal in design and automation of electronic systems. It publishes innovative work documenting significant research and development advances on the specification, design, analysis, simulation, testing, and evaluation of electronic systems, emphasizing a computer science/engineering orientation. Both theoretical analysis and practical solutions are welcome.
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