用于信号处理的高吞吐量 DWT 架构

N B V V S S Mani Manjari, Dr. S V R K RAO
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引用次数: 0

摘要

离散小波变换(DWT)在信号处理系统中至关重要,因为它能够准确记录频域和时域特征。然而,DWT 的计算复杂性给实时处理带来了明显的障碍,尤其是在数据消耗量较大的情况下。本研究提出了一种 VLSI 技术,旨在利用 CMOS 栅极加速 DWT 处理。其目标是在保持面积效率的同时提高吞吐量。该架构利用并行和流水线技术来利用 DWT 处理中的基本冗余。我们的重点是创建专门用于执行离散小波变换 (DWT) 操作的定制处理单元。我们对这些单元进行了调整,以最大限度地利用 CMOS 栅极能力。所提出的架构使用 Cadence virtuoso 软件实现,采用 45 纳米设计。根据其面积、功耗和延迟对其进行了评估。评估拟议设计所采用的当前技术包括利用 Radix-2 技术进行 FIR 滤波器设计,以及采用查找表携带选择加法器(LCSLA)、吠陀设计(VD)和携带前瞻加法器(CLA)。所开发的系统设计面积为 1764 um2,小于传统方法的面积。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
High Throughput DWT Architecture for Signal Processing
The Discrete Wavelet Transform (DWT) is essential in signal processing systems because it is capable of accurately recording both frequency and time-domain features. Nevertheless, the computational intricacy of DWT presents notable obstacles to processing in real-time, particularly in circumstances with large data consumption. This study presents a VLSI technology designed to accelerate DWT processing utilizing CMOS gates. The goal is to improve throughput while maintaining area efficiency. The architecture utilizes parallelism and pipelining techniques to take use of the fundamental redundancy in DWT processing. We focus on creating customized processing units developed specifically for performing Discrete Wavelet Transform (DWT) operations. These units are tuned to make the best possible usage of CMOS gate capabilities. The proposed architectural is implemented using Cadence virtuoso software with 45 nm design. It is evaluated based on its area, power consumption, and latency. The current techniques employed to assess the proposed design include the utilization of the Radix-2 technique for FIR filter design, as well as the employment of look-up-table carry select adder (LCSLA), Vedic design (VD), and carry look-ahead adder (CLA). The developed system design has an area of 1764 um2, which makes it smaller than that of conventional approaches.
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