Assessment of vertical shifted carrier schemes for sinusoidal pulsewidth modulation

The carrier modulated sinusoidal pulsewidth modulation scheme has been acknowledged for its fundamental fortification and harmonic reduction in DC–AC conversion. This study is focused on how to get a variable output voltage with the least harmonics by changing the amplitude of the carrier wave vertically instead of modulating the reference wave (conventional SPWM). This paper proposes four control schemes for achieving the maximum fundamental voltage in a three phase voltage source inverter. The four schemes are single edge carrier shifted with (i) fixed reference and (ii) variable reference, and double edge carrier shifted with (iii) fixed reference and (iv) variable reference. In addition, the reverse modulation index and mutual modulation index are introduced as new control variables for examination. These schemes are simulated with a three phase inverter and the performance is compared with conventional sinusoidal pulsewidth modulation using MATLAB R2021. The amplitude of the fundamental voltage and the corresponding THD are reported. Digital implementations of the proposed schemes are premeditated by using VHDL language and ModelSim. The validity of the proposed schemes is experimentally investigated through a laboratory prototype of a three phase inverter module incorporated with an FPGA Spartan 6 device. This prototype is tested with a three phase induction motor as the load. The fundamental voltage and THD for the existing and proposed schemes are reported.