Design and Simulation of New High Speed, Low Power D-Flip-Flops, Implemented Using Graphene Nanoribbon and Carbon Nanotube Field Effect Transistors

A novel 13-transistor, low-power true single-phase clocked (TSPC) flip-flop design is proposed which improves clock loading, power consumption, and performance. The power reduction is achieved by applying the stackly arranged low power-on transistor technique to the last stage of the proposed TSPC flip-flop. The circuit is separately implemented using carbon nanotube field effect transistors (CNTFETs), and graphene nanoribbons field effect transistors (GNRFETs). Prior to the final simulations, the optimum parameters of the CNTFETs, and GNRFETs were determined by sweeping their respective design parameters such as oxide thicknesses, nanotube diameters, and the number of nanoribbons. The proposed circuit is then simulated using the optimum transistors. Results demonstrate power consumptions as low as 0.0303 μW and 0.0263 μW, for the CNTFET and GNRFET transistor implementations, respectively, which are at least 72.26% and 94.9% lower than the previously reported flip-flops. Furthermore, it is shown that the proposed flip-flop exhibits better power-delay products (1.830 aJ and 1.519 aJ for CNTFET, and GNRFET implementations, respectively), which are 56.22% and 97.83% lower than those of existing carbon-based or silicon-based designs. This suggests our carbon-based designs as a promising CMOS substitution for low-power, high-performance applications. Both implementations were also investigated for robustness against the variations of supply voltage and operating temperature, and the effects of physical parameters on CNTFET-based implementation were investigated using Monte Carlo analysis. It was shown that although the GNRFET implementation has slightly better performance, by having better power, speed, and PDP, the CNTFET remains completely robust over the simulated ranges of parameters.