An advanced encryption standard framework for coarse-grained reconfigurable processor

Currently, the Advanced Encryption Standard (AES) holds the distinction of being the most widely used symmetric cryptographic algorithm. The importance of developing AES with superior performance cannot be overstated, as it holds the potential to expand its vast range of applications. The encryption algorithm may leak some information during operation, which may be used by attackers for side channel attacks (SCA). CGRA (Coarse-Grained Reconfigurable Architecture), as a coarse-grained reconfigurable architecture, allows hardware resources to be reconfigured for different tasks. This reduces the impact of SCA during encryption and decryption. To improve the security of AES algorithm, this paper introduces an encryption and decryption framework based on open-source CGRA complier that enable domain experts to easily accelerate the plaintexts on reconfigurable processors. Firstly, we propose an improved hardware-friendly AES algorithm, which allows the processing elements (PE) of CGRA to access the data in a vectorized fashion. Secondly, a new set of CGRA instructions, based on the proposed algorithm, has been used and the performance has been improved up to 19 times when compared to the standard AES algorithm. Finally, we evaluate the proper size of CGRA to balance the performance and the area. Our experiments show that the best compromise of CGRA size is 8 * 8 for classic AES-128.