Maciej Kamiński, Andrzej Taube, Jarosław Tarenko, Oskar Sadowski, Ernest Brzozowski, Justyna Wierzbicka, Magdalena Zadura, Marek Ekielski, K. Kosiel, Joanna Jankowska‐Śliwińska, Kamil Abendroth, Anna Szerling, P. Prystawko, Michał Boćkowski, I. Grzegory
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引用次数: 0
摘要
本文报告了在氨热法生长的块状氮化镓衬底上制造垂直氮化镓沟槽-MOSFET的过程和特性。该研究开发了一系列技术工艺,包括 Ga 面 n-GaN 外延层的低电阻欧姆接触、N 面背面欧姆接触、垂直侧壁沟槽蚀刻工艺、表面制备以及栅极介电层的原子层沉积,并与垂直功率器件的制造工艺流程相结合。制造出的测试结构的输出漏极电流为 288 ± 74 mA mm-1,阈值电压约为 10 V,场效应沟道迁移率在 10 V 漏极-源极电压下为 13.1 ± 5.0 cm2 (Vs)-1,在 0.1 V 漏极-源极电压下高达 65 cm2 (Vs)-1。此外,还首先进行了大电流多胞晶体管制造实验。成功制作并表征了具有六边形拓扑结构、总栅极宽度为 11.1 mm、输出电流超过 1 A 的多单元测试器件。
Vertical GaN Trench‐MOSFETs Fabricated on Ammonothermally Grown Bulk GaN Substrates
Herein, the fabrication and characterization of vertical GaN trench‐MOSFETs on ammonothermally grown bulk GaN substrates have been reported. A number of technological processes have been developed, including, among others, low‐resistance ohmic contacts to Ga‐face n‐GaN epitaxial layers, N‐face backside ohmic contact, vertical sidewall trench etching processes, surface preparation, and atomic layer deposition of gate dielectric layers and integrated with fabrication process flow of vertical power devices. The fabricated test structures are characterized by an output drain current of 288 ± 74 mA mm−1, threshold voltage of about 10 V, and field‐effect channel mobility 13.1 ± 5.0 cm2 (Vs)−1 at 10 V drain‐source voltage and up to 65 cm2 (Vs)−1 at 0.1 V drain‐source voltage. In addition, first, experiments toward high current multicell transistor fabrication are carried out. Multicell test devices with hexagonal topology with a total gate width of 11.1 mm and output current over 1 A are successfully fabricated and characterized.