RCVM-ASS-CICSKA-PAPT-VDF: VLSI design of high-speed reconfigurable compressed Vedic PAPT-VDF filter for ECG medical application

During signal acquisition, the signals are impacted by multiple noise sources that must be filtered before any analysis. However, many different filter implementations in VLSI are dispersed among many studies. This study aims to give readers a systematic approach to designing a Pipelined All-Pass Transformation based Variable digital filter (PAPT-VDF) to eliminate the high-frequency noise from ECG data. The modified design emphasizes first- and second-order responses to obtain high-speed filter realization with high operating frequencies. The addition of adder and multiplier designs to the hardware architecture of a filter design improves performance. The fundamental blocks of the filter design are the adder and multiplier. The adder and multiplier are employed with an Adaptable stage size-based concatenation, incremented carry-skip adder (ASS-CICSKA), and Improved reconfigurable compressed Vedic multiplier (IRCVM). Utilizing the adder design diminishes the delay with enhanced performance because receiving the carry from an incrementation block is not mandatory. In the multiplier design, the compressor and the reconfigurable approach are adapted with a data detector block to detect the redundant input and lower the logic gates' switching activity with less area overhead. The proposed filter design is implemented in vertex 7 FPGA family device, and the performance measures are analyzed regarding area utilization, delay, power, and frequency. Also, by using the denoised signal, the mean square error (MSE), and signal-to-noise ratio (SNR) are evaluated in the MATLAB platform.