Optimizing time resolution and power consumption in a current-mode circuit for SiPMs

Several applications that employ SiPMs require high time precision readout electronics. This work presents a study for the optimization of timing resolution of readout electronics for SiPMs focused on the effect of sensor area, transistor scaling and power consumption on electronic jitter. The design of the most critical stages are presented, specially the front-end input stage in current-mode. The performance of three different technologies (180, 130 and 65 nm) are studied. 65 nm is the best option to obtain good timing resolution with less power consumption. Dividing the sensor into smaller segments improves the Single Photon Electronics Jitter (SPEJ), but does not translate into a better Coincidence Time Resolution (CTR) when keeping the power per unit area constant, performing analog summation or employing an averaging algorithm of the time stamps for small LSO:Ce:%0.2Ca scintillator crystal.