FastRICH 的模拟前端：用于 LHCb RICH 探测器升级的 ASIC

Journal of Instrumentation Pub Date : 2024-04-01 DOI:10.1088/1748-0221/19/04/c04030

R. Manera, R. Ballabriga, J. Mauricio, J. Kaplon, A. Paternò, F. Bandi, S. Gómez, A. Pulli, S. Portero, J. Silva, F. Keizer, C. D’Ambrosio, M. Campbell, D. Gascón

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引用次数: 0

摘要

这项工作介绍了FastRICH ASIC的模拟电路，这是一个16通道ASIC，采用65纳米CMOS技术开发，专门为大型强子对撞机b的RICH探测器设计，用于读出探测器，如将在大型强子对撞机第4运行阶段使用的光电倍增管和第5运行阶段的候选硅光电倍增管。前端（FE）级的输入阻抗低于 50 Ω，输入动态范围为 5 μA 至 5 mA，功耗为 5 mW/通道。该芯片包括一个前沿比较器 (LED) 和一个用于时间拾取的恒分数鉴频器 (CFD)，以及一个用于数字化的时间数字转换器 (TDC)。

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The analog front end for FastRICH: an ASIC for the LHCb RICH detector upgrade

This work presents the analog circuitry of the FastRICH ASIC, a 16-channel ASIC, developed in a 65 nm CMOS technology specifically designed for the RICH detector at LHCb to readout detectors like Photomultiplier Tubes to be used at the LHC Run 4 and Silicon Photomultipliers candidates for Run 5. The front-end (FE) stage has an input impedance below 50 Ω and an input dynamic range from 5 μA to 5 mA with a power consumption of ∼5 mW/channel. The chip includes a Leading Edge Comparator (LED) and a Constant Fraction Discriminator (CFD) for time pick-off and a Time-to-Digital Converter (TDC) for digitization.

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Journal of Instrumentation

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