利用 TiO2/HfO2 晶闸管交叉棒的非线性传导特性实现并行矢量矩阵乘法

Wei Wei, Cong Wang, Chen Pan, Xing-Jian Yangdong, Zaizheng Yang, Yuekun Yang, Bin Cheng, Shi-Jun Liang, Feng Miao
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引用次数: 0

摘要

通过就地实现并行向量矩阵乘法(VMM),忆阻器横杆阵列有望实现高能效的神经形态计算。忆阻器与神经突触之间的相似性为实现基于硬件的大脑启发计算(如尖峰神经网络)提供了机会。然而,忆阻器的非线性 I-V 特性限制了在无源忆阻器交叉棒阵列上实现并行 VMM。在我们的工作中,我们提议利用差分电导作为突触权重,在被动忆阻器阵列上并行实施线性 VMM 操作。我们制作了一个二氧化钛/二氧化氢忆阻器交叉棒阵列,其中基于差分电导的突触权重具有可塑性、非波动性、多态性和可调的导通/关断比。我们评估了基于所提方法的 VMM 操作随噪声变化的精度性能,为优化提供了指导。此外,我们还展示了一种尖峰神经网络电路,它能够通过基于差分电导的突触处理小尖峰信号。实验结果展示了有效的空间编码和时间编码尖峰模式识别。重要的是,我们的工作为无源忆阻器阵列的开发开辟了新的可能性,从而提高了脑启发芯片的能量和面积效率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Harnessing nonlinear conductive characteristic of TiO2/HfO2 memristor crossbar for implementing parallel vector–matrix multiplication
Memristor crossbar arrays are expected to achieve highly energy-efficient neuromorphic computing via implementing parallel vector–matrix multiplication (VMM) in situ. The similarities between memristors and neural synapses offer opportunities for realizing hardware-based brain-inspired computing, such as spike neural networks. However, the nonlinear I–V characteristics of the memristors limit the implementation of parallel VMM on passive memristor crossbar arrays. In our work, we propose to utilize differential conductance as a synaptic weight to implement linear VMM operations on a passive memristor array in parallel. We fabricated a TiO2/HfO2 memristor crossbar array, in which differential-conductance-based synaptic weight exhibits plasticity, nonvolatility, multi-states, and tunable ON/OFF ratio. The noise-dependent accuracy performance of VMM operations based on the proposed approach was evaluated, offering an optimization guideline. Furthermore, we demonstrated a spike neural network circuit capable of processing small spiking signals through the differential-conductance-based synapses. The experimental results showcase effective space-coded and time-coded spike pattern recognition. Importantly, our work opens up new possibilities for the development of passive memristor arrays, leading to increased energy and area efficiency in brain-inspired chips.
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