高掺杂基底上的低温金属氧化物半导体器件中跳变现象引起的虚阻抗和掺杂离子化时间评估

Tomohisa Miyao, Keito Yoshinaga, Takahisa Tanaka, Hiroki Ishikuro, Munehiro Tada, Ken Uchida
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引用次数: 0

摘要

在掺杂浓度高达 1018 cm-3 的衬底上制造的 MOS 电容器在 4.2 K 下进行了表征。高掺杂衬底在 4.2 K 下表现出固有的阻抗虚分量。此外,我们还研究了耗尽条件下与掺杂电离相关的时间常数,并确定其为 0.35 μs。图中还显示了高掺杂基底在 4.2 K 时的等效电路模型。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Imaginary impedance due to hopping phenomena and evaluation of dopant ionization time in cryogenic metal-oxide-semiconductor devices on highly doped substrate
MOS capacitors fabricated on substrates with doping concentrations as high as 1018 cm-3 were characterized at 4.2 K. The highly doped substrate exhibited an intrinsic imaginary component of impedance at 4.2 K. The imaginary component is attributed to the time delay induced by hopping phenomena, leading to a decrease in the gate capacitance. Furthermore, we investigated the time constant associated with dopant ionization under depletion conditions and determined it to be 0.35 μs. An equivalent circuit model of the highly doped substrate at 4.2 K is also shown.
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