利用 CXL 共享内存：硬件和软件设计方法

arXiv - CS - Operating Systems Pub Date : 2024-04-04 DOI:arxiv-2404.03245

Sunita Jain, Nagaradhesh Yeleswarapu, Hasan Al Maruf, Rita Gupta

{"title":"利用 CXL 共享内存：硬件和软件设计方法","authors":"Sunita Jain, Nagaradhesh Yeleswarapu, Hasan Al Maruf, Rita Gupta","doi":"arxiv-2404.03245","DOIUrl":null,"url":null,"abstract":"Compute Express Link (CXL) is a rapidly emerging coherent interconnect\nstandard that provides opportunities for memory pooling and sharing. Memory\nsharing is a well-established software feature that improves memory utilization\nby avoiding unnecessary data movement. In this paper, we discuss multiple\napproaches to enable memory sharing with different generations of CXL protocol\n(i.e., CXL 2.0 and CXL 3.0) considering the challenges with each of the\narchitectures from the device hardware and software viewpoint.","PeriodicalId":501333,"journal":{"name":"arXiv - CS - Operating Systems","volume":"68 1","pages":""},"PeriodicalIF":0.0000,"publicationDate":"2024-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Memory Sharing with CXL: Hardware and Software Design Approaches\",\"authors\":\"Sunita Jain, Nagaradhesh Yeleswarapu, Hasan Al Maruf, Rita Gupta\",\"doi\":\"arxiv-2404.03245\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Compute Express Link (CXL) is a rapidly emerging coherent interconnect\\nstandard that provides opportunities for memory pooling and sharing. Memory\\nsharing is a well-established software feature that improves memory utilization\\nby avoiding unnecessary data movement. In this paper, we discuss multiple\\napproaches to enable memory sharing with different generations of CXL protocol\\n(i.e., CXL 2.0 and CXL 3.0) considering the challenges with each of the\\narchitectures from the device hardware and software viewpoint.\",\"PeriodicalId\":501333,\"journal\":{\"name\":\"arXiv - CS - Operating Systems\",\"volume\":\"68 1\",\"pages\":\"\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2024-04-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"arXiv - CS - Operating Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/arxiv-2404.03245\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"arXiv - CS - Operating Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/arxiv-2404.03245","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

Compute Express Link（CXL）是一种迅速崛起的相干互连标准，为内存池和共享提供了机会。内存共享是一种成熟的软件功能，可通过避免不必要的数据移动提高内存利用率。在本文中，我们从设备硬件和软件的角度出发，讨论了利用不同世代的 CXL 协议（即 CXL 2.0 和 CXL 3.0）实现内存共享的多种方法，并考虑了每种架构所面临的挑战。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Memory Sharing with CXL: Hardware and Software Design Approaches

Compute Express Link (CXL) is a rapidly emerging coherent interconnect standard that provides opportunities for memory pooling and sharing. Memory sharing is a well-established software feature that improves memory utilization by avoiding unnecessary data movement. In this paper, we discuss multiple approaches to enable memory sharing with different generations of CXL protocol (i.e., CXL 2.0 and CXL 3.0) considering the challenges with each of the architectures from the device hardware and software viewpoint.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

arXiv - CS - Operating Systems

自引率

0.00%

发文量