霍尔传感器读出集成电路的 CMOS 模拟前端

2024 International Conference on Electronics, Information, and Communication (ICEIC) Pub Date : 2024-01-28 DOI:10.1109/ICEIC61013.2024.10457102

Kang-Il Cho, Jun-Ho Boo, Jae-Geun Lim, Gil-Cho Ahn

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引用次数: 0

摘要

本文介绍了一种用于霍尔传感器读出集成电路的 CMOS 模拟前端（AFE）。它采用了一个基于三运算放大器的仪表放大器 (IA)，以实现具有高共模抑制比的低噪声放大。为解决霍尔磁传感器的输入偏移问题，采用了一个使用 R-2R DAC 的内部偏移消除电路。二阶增量式 ADC 用于将放大的模拟输入转换为 16 位数字输出。拟议的 AFE 采用 80 纳米 CMOS 工艺实现。在电压增益为 40V/V 时，输出噪声功率为 6.8nV2，2.8V 电源功耗为 16.8mW。

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A CMOS Analog Front-End for Hall Sensor Readout IC

This paper presents a CMOS analog front-end (AFE) for hall sensor readout IC. A three- operational amplifier-based instrumentation amplifier (IA) is employed for low noise amplification with high common mode rejection ratio. To address the input offset of the hall magnetic sensor, an internal offset cancellation circuit using a R-2R DAC is adopted. A 2nd order incremental ADC is used to convert the amplified analog input into 16-bit digital output. The proposed AFE is implemented in an 80nm CMOS process. It achieves a 6.8nV2 of the output noise power at a voltage gain of 40V/V and consumes 16.8mW from a 2.8V power supply.

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2024 International Conference on Electronics, Information, and Communication (ICEIC)

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