{"title":"内存处理比特杯应用的软硬件协同仿真方法","authors":"Jae-Gun Lee, Shin-Uk Kang, Min-Seong Choo","doi":"10.1109/ICEIC61013.2024.10457160","DOIUrl":null,"url":null,"abstract":"This paper proposes a reliable design methodology for processing-in-memory (PIM) Macro design. Instead of focusing on neural network training and inferencing in full precision, whether deep neural network (DNN) or convolutional neural network (CNN), we present an efficient and accurate performance evaluation methodology through simulation that considers the characteristics of actual bitcells in use. Additionally, we suggest necessary hardware design constraints to achieve high accuracy.","PeriodicalId":518726,"journal":{"name":"2024 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"172 3","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2024-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Hardware and Software Co-Simulation Methodology for Processing-in-Memory Bitcell application\",\"authors\":\"Jae-Gun Lee, Shin-Uk Kang, Min-Seong Choo\",\"doi\":\"10.1109/ICEIC61013.2024.10457160\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a reliable design methodology for processing-in-memory (PIM) Macro design. Instead of focusing on neural network training and inferencing in full precision, whether deep neural network (DNN) or convolutional neural network (CNN), we present an efficient and accurate performance evaluation methodology through simulation that considers the characteristics of actual bitcells in use. Additionally, we suggest necessary hardware design constraints to achieve high accuracy.\",\"PeriodicalId\":518726,\"journal\":{\"name\":\"2024 International Conference on Electronics, Information, and Communication (ICEIC)\",\"volume\":\"172 3\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2024-01-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2024 International Conference on Electronics, Information, and Communication (ICEIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICEIC61013.2024.10457160\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2024 International Conference on Electronics, Information, and Communication (ICEIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEIC61013.2024.10457160","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Hardware and Software Co-Simulation Methodology for Processing-in-Memory Bitcell application
This paper proposes a reliable design methodology for processing-in-memory (PIM) Macro design. Instead of focusing on neural network training and inferencing in full precision, whether deep neural network (DNN) or convolutional neural network (CNN), we present an efficient and accurate performance evaluation methodology through simulation that considers the characteristics of actual bitcells in use. Additionally, we suggest necessary hardware design constraints to achieve high accuracy.