设计具有电源噪声补偿功能的低抖动数字控制振荡器

2024 International Conference on Electronics, Information, and Communication (ICEIC) Pub Date : 2024-01-28 DOI:10.1109/ICEIC61013.2024.10457171

Min-Ji Kim, Won-Young Lee

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引用次数: 0

摘要

本文提出了一种采用补偿器技术的时钟缓冲器，以实现数字控制振荡器（DCO）的低抖动设计。补偿器由一个 PMOS 晶体管和一个 MOS 电容器组成。提供与延迟单元相反灵敏度的补偿器连接到每个延迟单元之间的节点上。在 ±0.1% VDD 噪声条件下，基于 3 GHz 输出频率，补偿后的 DCO 抖动降低了约 12.7-ps（峰峰值）。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design of a Low-Jitter Digitally Controlled Oscillator With Supply Noise Compensation

This paper proposes a clock buffer with compensator technology to achieve low-jitter design in the digitally controlled oscillator (DCO). The compensator consists of a PMOS transistor and a MOS capacitor. The compensator that provides the opposite sensitivity to the delay cell is connected to the node between each delay cell. The compensated DCO has a reduced jitter of approximately 12.7-ps (peak-to-peak) based on the 3-GHz output frequency under ±0.1% VDD noise.

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来源期刊

2024 International Conference on Electronics, Information, and Communication (ICEIC)

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