在先进 CMOS 技术中制作 k 值可调的低 k 薄膜作为间隔物

Lewen Qian, Xin Sun, Tao Liu, Ziqiang Huang, Xinlong Guo, Maolin Pan, Dawei Wang, Saisheng Xu, Min Xu, Chen Wang, Chunlei Wu, David Wei Zhang
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引用次数: 0

摘要

在先进的 CMOS 技术中,一个合适的隔层方案对于缓解临界尺寸缩小时寄生电阻和电容增加对器件性能的影响至关重要。利用等离子体增强原子层沉积技术在单室中制造出了低介电常数(低 k)薄膜,其 k 值可调,范围在 3.5 到 6.5 之间。制备过程包括在 N2 等离子体中通过 SiH2I2 沉积 SiN 薄膜,以及在 O2、Ar/O2 和 N2/O2 等离子体中分别使用二异丙基氨基硅烷沉积 SiOX、SiOCN 和 SiON 薄膜。引入含碳(C)的基团后,由于碳与硅的结合强度较弱,薄膜结构趋于松散,因此在结构和电气稳定性方面有所区别。我们开发了这样一种工艺,可以通过调节 C 基团浓度和 O、N 含量来调整薄膜的 k 值。SiOx、SiOCN、SiON 和 SiN 薄膜的击穿强度分别为 9.04、7.23、9.41 和超过 11 MV cm-1,同时漏电流密度分别为 2.42 × 10-9、4.78 × 10-8、1.29 × 10-9 和 9.26 × 10-10 A cm-2。这些薄膜表现出显著的热稳定性,击穿强度增强,退火处理后漏电抑制,这可能归功于 -CHX 基团的解吸。此外,低 k 材料在内层间隔腔和侧壁上都表现出了极好的阶跃覆盖性,从而探索了在先进 CMOS 结构中用作间隔层的潜在应用。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Fabrication of the low-k films with tunable k value as spacers in advanced CMOS technology
In advanced CMOS technology, a suitable spacer scheme is crucial to alleviate the effects of increasing parasitic resistance and capacitance on device performance as the critical dimensions shrinking. Low dielectric constant (low-k) films, possessing a tunable k value ranging from 3.5 to 6.5, were fabricated using plasma-enhanced atomic layer deposition in a single chamber. The fabrication process involved the deposition of the SiN film via SiH2I2 with N2 plasma, as well as the deposition of the SiOX, SiOCN, and SiON films using diisopropylamino silane with O2, Ar/O2, and N2/O2 plasmas, respectively. The introduction of groups containing carbon (C) tended to loosen the film structure, due to its weak bond strength with Si, thus made distinctions in structural and electrical stability. We developed such a process which can adjust the C-group concentration and O, N content to tune the film k value. The SiOx, SiOCN, SiON, and SiN films had high breakdown strength of 9.04, 7.23, 9.41, and over 11 MV cm−1, and meanwhile low leakage current density of 2.42 × 10−9, 4.78 × 10−8, 1.29 × 10−9, and 9.26 × 10−10 A cm−2, respectively. The films exhibited remarkable thermal stability, enhanced breakdown strength, and suppressed leakage with annealing treatment, which could be attributed to the desorption of —CHX groups. Moreover, the low-k materials demonstrated excellent step coverage both in the inner-spacer cavity and on sidewalls, exploring the potential application as spacers in advanced CMOS structure.
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