A Low Power R-peak Detector Clocked at Signal Sampling Rate

This paper presents a real-time, low-power R-peak detector implemented in an FPGA. It is different from other implementations as it runs at the same signal sampling rate, rather than utilizing a high clock frequency as utilized in batch processing with high throughput systems. Such implementation relies on a Savitzky-Golay filter for power line noise filtering, and on an adapted version of the Difference Operation Method (DOM) algorithm. The modification in DOM is needed in order to be able to process the data either without increasing the clock to process data in a batch fashion or unsustainably increasing latency. It uses the Savitzky-Golay Digital Differentiator, eliminating further filtering stages. The prototype was characterized using both the MIT-BIH database and Fluke Prosim 8 Vital Signal Simulator. The proposed system features a high degree of matched R-peaks even being extremely efficient regarding power dissipation. Moreover, it shows similar performance when compared to the original Difference Operation Method implementation.The whole system consumes 260- uW operating at 192-Hz in an FPGA model 10M50DAF484C7G, which belongs to the MAX10 family of Altera devices.